RISC-V ISA Explorer

An interactive reference for RISC-V extensions, profiles and per-instruction encodings. Pick a base ISA or a ratified profile, add extensions, and get a dependency-resolved configuration with a valid -march string.

The catalogue lists 211 extensions:

Base ISA

• RV32I: Standard Integer Base (32-bit)
• RV64I: Standard Integer Base (64-bit)
• RV32E: Embedded Base (16 regs)
• RV64E: Embedded Base (64-bit, 16 regs)
• RV128I: 128-bit Address Space

Single-Letter Extensions

• A: Atomics Bundle
• B: Bit-Manip Bundle
• C: Compressed
• D: Double-Precision Float (64-bit)
• F: Single-Precision Float (32-bit)
• H: Hypervisor
• M: Integer Multiply/Divide
• N: User-Level Interrupts
• P: Packed-SIMD
• Q: Quad-Precision Float (128-bit)
• S: Supervisor ISA
• U: User ISA
• V: Vector (RVV)
• Sm: Machine ISA

Bit Manipulation (Zb*)

• Zba: Address-Generation Bitmanip
• Zbb: Basic Bitmanip
• Zbc: Carry-less Multiply
• Zbs: Single-Bit Ops

Atomics (Za/Zic*)

• Za128rs: 128B Reservation Set
• Za64rs: 64B Reservation Set
• Zaamo: Atomic Memory Operations
• Zabha: Byte/Halfword AMO
• Zacas: Atomic Compare-and-Swap
• Zalasr: Load-Acquire/Store-Release
• Zalrsc: LR/SC Extension
• Zama16b: 16B Misaligned Atomicity
• Zawrs: Wait-on-Reservation-Set
• Ziccrse: LR/SC Forward Progress

Compressed (Zc*)

• Zca: Base Compressed (no FP)
• Zcb: Extra Compressed Integer
• Zcd: Compressed Double Float
• Zce: Embedded Compressed
• Zcf: Compressed Float Load/Store
• Zcmp: Push/Pop & Reg Save/Restore
• Zcmt: Compressed Table Jumps
• Zcmop: Compressed May-Be-Ops
• Zclsd: Compressed LS-Pair

Float & Numerics (Zf*)

• Zdinx: FP in Integer Regs (D)
• Zfa: Additional FP Instructions
• Zfbfmin: Minimal BF16 FP
• Zfh: Half-Precision FP (16-bit)
• Zfhmin: Minimal Half-Precision FP
• Zfinx: FP in Integer Regs (F)
• Zhinx: FP in Integer Regs (Half)
• Zhinxmin: Minimal Half-in-Int

Load / Store

• Zicclsm: Misaligned L/S Support
• Zilsd: Load/Store Pair for RV32

Integer

• Zibi: Branch with Immediate
• Zicond: Integer Conditional Ops
• Zmmul: Multiply-Only (no DIV)

Vector Subsets (Zv/Zve)

• Zve32x: Vec Int (32-bit, embedded)
• Zve32f: Vec FP32 (embedded)
• Zve64x: Vec Int (64-bit, embedded)
• Zve64f: Vec FP32+Int (64-bit, embedded)
• Zve64d: Vec FP64+FP32+Int
• Zvl32b: Min VLEN ≥ 32b
• Zvl64b: Min VLEN ≥ 64b
• Zvl128b: Min VLEN ≥ 128b
• Zvl256b: Min VLEN ≥ 256b
• Zvl512b: Min VLEN ≥ 512b
• Zvl1024b: Min VLEN ≥ 1024b
• Zvfh: Vector Half-Precision FP
• Zvfhmin: Vector Half-Precision Minimal
• Zvfbfmin: Vector BF16 Minimal
• Zvfbfa: Vector BF16 Arithmetic
• Zvfbfwma: Vector BF16 Widening MAC
• Zvfofp8min: Vector FP8 Minimal
• Zvabd: Vector Abs-Diff
• Zvbb: Vector Bitmanip Base
• Zvbc: Vector Carryless Multiply
• Zvbdota: Vector BF16 Dot-Acc
• Zvdota: Vector Dot-Acc
• Zvdot4a: Vector 4-way Dot-Acc

Security & CFI

• Smcfiss: M-Mode Shadow Stack
• Zicfilp: CFI Landing Pads
• Zicfiss: CFI Shadow Stacks

Cryptography (Zk*)

• Zbkb: Crypto Bitmanip
• Zbkc: Crypto Bitmanip (carryless)
• Zbkx: Crypto Bitmanip (crossbar)
• Zk: Scalar Crypto Base
• Zkn: NIST Suite (Scalar)
• Zknd: NIST AES Decrypt
• Zkne: NIST AES Encrypt
• Zknh: NIST Hash
• Zkr: Entropy Source
• Zks: ShangMi Suite (Scalar)
• Zksed: SM4 Block Cipher
• Zksh: SM3 Hash
• Zkt: Timing-Safe Crypto

Vector Cryptography (Zvk*)

• Zvbc32e: Vector CLMUL (32E)
• Zvkb: Vector Crypto Bitmanip
• Zvkg: Vector GCM/GMAC
• Zvkgs: Vector GCM Shim
• Zvkn: Vector NIST Suite
• Zvknc: Vector NIST + CLMUL
• Zvkned: Vector AES
• Zvknf: Vector AES Finite-field
• Zvkng: Vector NIST + GCM
• Zvknha: Vector SHA-2 (subset)
• Zvknhb: Vector SHA-2 (full)
• Zvks: Vector ShangMi Suite
• Zvksc: Vector ShangMi + CLMUL
• Zvksed: Vector SM4
• Zvksg: Vector ShangMi + GCM
• Zvksh: Vector SM3 Hash
• Zvkt: Vector Timing-Safe Crypto

System

• Zicntr: Base Counters/Timers
• Zicsr: CSR Access
• Zifencei: Instruction-Fetch Fence
• Zihintntl: Non-Temporal Locality Hints
• Zihintpause: Pause Hint
• Zihpm: Perf Counters
• Zimop: May-Be-Ops (NOP family)
• Zimt: Memory Tagging
• Zjid: ICache Coherence Alt
• Zjpm: Pointer-Mask Qualifier
• Ztso: Total Store Ordering

Caches

• Zic64b: 64B Cache Blocks
• Zicbom: Cache Management Operations
• Zicbop: Cache Prefetch
• Zicboz: Cache Block Zero
• Ziccamoa: Atomics PMA
• Ziccamoc: CAS PMA
• Ziccid: Instruction/Data Coherence
• Ziccif: Inst-Fetch Atomicity

Memory & Addressing

• Sv32: Virtual Memory, 32-bit
• Sv39: Virtual Memory, 39-bit VA
• Sv48: Virtual Memory, 48-bit VA
• Sv57: Virtual Memory, 57-bit VA
• Svbare: Bare Mode
• Svpbmt: Page-Based Memory Types
• Svnapot: NAPOT Mappings
• Svinval: Fine-Grained TLB Invalidate
• Svade: Access/Dirty Exceptions
• Svadu: Access/Dirty Update
• Svvptc: Visible PTE Changes
• Svrsw60t59b: PTE RSW Bits
• Svatag: Tagged Translations
• Svukte: Constant-Time User Faults
• Supm: User Pointer Masking
• Ssnpm: Supervisor Next-Pointer Mask
• Sspm: Supervisor Pointer Masking
• Ssccptr: Page-Table Reads in Main Memory
• Smvatag: VA Tagging (M)
• Smepmp: Enhanced PMP
• Smmpm: Pointer Masking (M-mode)
• Smnpm: Pointer Masking (next mode)
• Smpmpmt: PMP-Based Memory Types
• Sspmp: S-level PMP
• Sspmpen: SPMP Entry Enable
• Smpmpdeleg: PMP/SPMP Sharing

Interrupts (Sm/Ss)

• Smaia: AIA Machine Extension
• Ssaia: AIA Supervisor Extension
• Smclic: Machine CLIC
• Smclicconfig: Machine CLIC Config
• Smclicshv: Machine CLIC SHV
• Ssclic: Supervisor CLIC
• Suclic: User CLIC
• Sstc: Supervisor Timer Compare
• Sscofpmf: Counter Overflow & Filtering
• Shlcofideleg: Counter Overflow Delegation
• Ssqosid: QoS Identifiers
• Smrnmi: Resumable NMI
• Smsdia: Soft Debug/Instr

Counters & Profiling

• Smcdeleg: M-Mode Counter Delegation
• Smcntrpmf: M-Mode Counter Filtering
• Ssccfg: Counter Configuration (S)
• Sscounterenw: Writable scounteren

Traps

• Sdext: External Debug
• Sdtrig: Debug Triggers
• Sdtrigepm: Debug Trigger EPM
• Sdtrigpend: Debug Trigger Pending
• Smcsrind: Indirect CSR Access (M)
• Sscsrind: Indirect CSR Access (S)
• Smctr: Control Transfer Records (M)
• Ssctr: Control Transfer Records (S)
• Sddbltrp: Debug Double Trap
• Ssdbltrp: Supervisor Double Trap
• Smdbltrp: Machine Double Trap
• Smstateen: M-Mode State Enable
• Ssstateen: S-Mode State Enable
• Sm1p11: Priv Spec M v1.11
• Ss1p11: Priv Spec S v1.11
• Sm1p12: Priv Spec M v1.12
• Ss1p12: Priv Spec S v1.12
• Sm1p13: Priv Spec M v1.13
• Ss1p13: Priv Spec S v1.13
• Sstvala: stval Address Rule
• Sstvecd: stvec Direct Mode
• Sstvecv: stvec Vectored Mode
• Ssdtso: Supervisor TSO Opt-in
• Sstcfg: Trap Config
• Ssstrict: No Non-Conforming Exts
• Ssu32xl: UXL=32 support
• Ssu64xl: UXL=64 support
• Ssube: Big-Endian S
• Smtdeleg: Trap Delegation
• RERI: RAS Error Reporting
• HTI: Hart-to-Trace Encoder Interface
• Sha: Augmented hypervisor
• Shcounterenw: Hypervisor counter enable
• Shgatpa: SvNNx4 guest translation for all supported S-mode modes, plus Bare
• Shtvala: Hypervisor Trap Value (htval) provides all needed values
• Shvsatpa: Virtual Supervisor address translation supports all supported S-mode modes
• Shvstvala: Virtual Supervisor Trap Value (vstval) provides all needed values
• Shvstvecd: Virtual Supervisor Trap Vector (vstvec) supports Direct mode