RISC-V ISA Explorer · Traps
Sdext: External Debug
Ratified 2025-02 · version 1.0.0
Hart-side half of external debug: Debug Mode entry, halt and resume, and the dcsr and dpc registers.
Typical use: Attaching an external debugger
Open Sdext in the explorerInstructions (1)
| Mnemonic | Name | Encoding | Match | Mask |
|---|---|---|---|---|
DRET | Return from Debug Mode | 01111011001000000000000001110011 | 0x7b200073 | 0xffffffff |
Control and status registers (4)
| Name | Address | Mode | Description |
|---|---|---|---|
dcsr | 0x7b0 | D | Debug Control and Status Register |
dpc | 0x7b1 | D | Debug PC Register |
dscratch0 | 0x7b2 | D | Debug scratch register |
dscratch1 | 0x7b3 | D | Debug scratch register |