RISC-V ISA Explorer · Traps
Sdtrig: Debug Triggers
Ratified 2025-02 · version 1.0.0
Hardware breakpoints and watchpoints that fire on instruction or load/store addresses without patching code.
Typical use: Breakpoints and watchpoints
Open Sdtrig in the explorerInstructions
No instruction encodings are listed for this extension in the catalogue.
Control and status registers (12)
| Name | Address | Mode | Description |
|---|---|---|---|
hcontext | 0x6a8 | S | Hypervisor Context |
hstateen0 | 0x60c | S | Hypervisor State Enable 0 Register |
hstateen0h | 0x61c | S | Upper 32 bits of Hypervisor State Enable 0 Register |
mcontext | 0x7a8 | M | Machine Context |
mscontext | 0x7aa | S | Machine Supervisor Context |
mstateen0 | 0x30c | M | Machine State Enable 0 Register |
mstateen0h | 0x31c | M | Upper 32 bits of Machine State Enable 0 Register |
scontext | 0x5a8 | S | Supervisor Context |
tdata1 | 0x7a1 | M | Trigger Data 1 |
tdata2 | 0x7a2 | M | Trigger Data 2 |
tdata3 | 0x7a3 | M | Trigger Data 3 |
tselect | 0x7a0 | M | Trigger Select |