RISC-V ISA Explorer · Traps
Smstateen: M-Mode State Enable
Ratified 2024-03 · version 1.0.0
Lets M-mode withhold access to state added by other extensions, so unaware software cannot leak or corrupt it.
Typical use: Gate access to extension CSRs
Open Smstateen in the explorerInstructions
No instruction encodings are listed for this extension in the catalogue.
Control and status registers (20)
| Name | Address | Mode | Description |
|---|---|---|---|
hstateen0 | 0x60c | S | Hypervisor State Enable 0 Register |
hstateen0h | 0x61c | S | Upper 32 bits of Hypervisor State Enable 0 Register |
hstateen1 | 0x60d | S | Hypervisor State Enable 1 Register |
hstateen1h | 0x61d | S | Upper 32 bits of Hypervisor State Enable 1 Register |
hstateen2 | 0x60e | S | Hypervisor State Enable 2 Register |
hstateen2h | 0x61e | S | Upper 32 bits of Hypervisor State Enable 2 Register |
hstateen3 | 0x60f | S | Hypervisor State Enable 3 Register |
hstateen3h | 0x61f | S | Upper 32 bits of Hypervisor State Enable 3 Register |
mstateen0 | 0x30c | M | Machine State Enable 0 Register |
mstateen0h | 0x31c | M | Upper 32 bits of Machine State Enable 0 Register |
mstateen1 | 0x30d | M | Machine State Enable 1 Register |
mstateen1h | 0x31d | M | Upper 32 bits of Machine State Enable 1 Register |
mstateen2 | 0x30e | M | Machine State Enable 2 Register |
mstateen2h | 0x31e | M | Upper 32 bits of Machine State Enable 2 Register |
mstateen3 | 0x30f | M | Machine State Enable 3 Register |
mstateen3h | 0x31f | M | Upper 32 bits of Machine State Enable 3 Register |
sstateen0 | 0x10c | S | Supervisor State Enable 0 Register |
sstateen1 | 0x10d | S | Supervisor State Enable 1 Register |
sstateen2 | 0x10e | S | Supervisor State Enable 2 Register |
sstateen3 | 0x10f | S | Supervisor State Enable 3 Register |