RISC-V ISA Explorer · Interrupts (Sm/Ss)
Ssaia: AIA Supervisor Extension
Ratified 2023-06 · version 1.0.0
Supervisor-level half of the Advanced Interrupt Architecture, exposing its CSRs and behavior below M-mode.
Typical use: Scalable interrupt delivery to supervisor
Open Ssaia in the explorerDependencies
Requires
Instructions
No instruction encodings are listed for this extension in the catalogue.
Control and status registers (4)
| Name | Address | Mode | Description |
|---|---|---|---|
hstateen0 | 0x60c | S | Hypervisor State Enable 0 Register |
hstateen0h | 0x61c | S | Upper 32 bits of Hypervisor State Enable 0 Register |
mstateen0 | 0x30c | M | Machine State Enable 0 Register |
mstateen0h | 0x31c | M | Upper 32 bits of Machine State Enable 0 Register |