RISC-V ISA Explorer · Traps
Sscsrind: Indirect CSR Access (S)
Ratified 2024-11 · version 1.0.0
Reaches large arrays of supervisor registers by index through a select and window CSR pair, saving CSR space.
Typical use: CSR indirection at S-mode
Open Sscsrind in the explorerDependencies
Requires
Required by
Instructions
No instruction encodings are listed for this extension in the catalogue.
Control and status registers (4)
| Name | Address | Mode | Description |
|---|---|---|---|
hstateen0 | 0x60c | S | Hypervisor State Enable 0 Register |
hstateen0h | 0x61c | S | Upper 32 bits of Hypervisor State Enable 0 Register |
mstateen0 | 0x30c | M | Machine State Enable 0 Register |
mstateen0h | 0x31c | M | Upper 32 bits of Machine State Enable 0 Register |