RISC-V ISA Explorer · Memory & Addressing
Sspmpen: SPMP Entry Enable
Ratified 2026-08 · version 1.0.0
A bitmask CSR that activates SPMP entries individually, so a context switch is one register write instead of reprogramming up to 128 registers.
Typical use: Cutting SPMP context-switch cost on RTOS workloads
Open Sspmpen in the explorerDependencies
Requires
Instructions
No instruction encodings are listed for this extension in the catalogue.
Control and status registers (2)
| Name | Address | Mode | Description |
|---|---|---|---|
spmpen | 0x183 | S | SPMP entry enable |
spmpenh | 0x193 | S | Upper 32 bits of SPMP entry enable (RV32 only) |