RISC-V ISA Explorer · Interrupts (Sm/Ss)

Sstc: Supervisor Timer Compare

Ratified 2024-03 · version 1.0.0

Lets S-mode and VS-mode set their own timer deadlines directly, avoiding a call down to machine-mode firmware.

Typical use: Per-hart timer interrupts

Specification

Instructions

No instruction encodings are listed for this extension in the catalogue.

Control and status registers (2)