RISC-V ISA Explorer · Memory & Addressing

Svinval: Fine-Grained TLB Invalidate

Ratified 2021-11 · version 1.0.0

Splits the SFENCE.VMA family into finer invalidate and ordering operations that pipeline better on wide cores.

Typical use: Fine-grain TLB shootdown instructions

Dependencies

Mnemonic	Name	Encoding	Match	Mask
`SFENCE.INVAL.IR`	Order implicit page table reads after invalidation	`00011000000100000000000001110011`	`0x18100073`	`0xffffffff`
`SFENCE.W.INVAL`	Order writes before sfence	`00011000000000000000000001110011`	`0x18000073`	`0xffffffff`
`SINVAL.VMA`	Invalidate cached address translations	`0001011----------000000001110011`	`0x16000073`	`0xfe007fff`