RISC-V ISA Explorer · System

Zicntr: Base Counters/Timers

Ratified 2019-12 · version 2.0.0

Unprivileged read access to the CYCLE, TIME and INSTRET counters for cycle count, real time and instructions retired.

Typical use: Cycle and instruction counting for profiling

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Dependencies

Requires

Zicsr

Instructions (6)

Mnemonic	Name	Encoding	Match	Mask
`RDCYCLE`		`11000000000000000010-----1110011`	`0xc0002073`	`0xfffff07f`
`RDCYCLEH`		`11001000000000000010-----1110011`	`0xc8002073`	`0xfffff07f`
`RDINSTRET`		`11000000001000000010-----1110011`	`0xc0202073`	`0xfffff07f`
`RDINSTRETH`		`11001000001000000010-----1110011`	`0xc8202073`	`0xfffff07f`
`RDTIME`		`11000000000100000010-----1110011`	`0xc0102073`	`0xfffff07f`
`RDTIMEH`		`11001000000100000010-----1110011`	`0xc8102073`	`0xfffff07f`

Control and status registers (7)

Name	Address	Mode	Description
`cycle`	`0xc00`	U	Cycle counter for RDCYCLE Instruction
`cycleh`	`0xc80`	U	High-half cycle counter for RDCYCLE Instruction
`instret`	`0xc02`	U	Instructions retired counter for RDINSTRET Instruction
`instreth`	`0xc82`	U	Instructions retired counter, high bits
`minstreth`	`0xb82`	M	Machine Instructions Retired Counter
`time`	`0xc01`	U	Timer for RDTIME Instruction
`timeh`	`0xc81`	U	High-half timer for RDTIME Instruction