RISC-V ISA Explorer · Vector Subsets (Zv/Zve)
Zvl1024b: Min VLEN ≥ 1024b
Ratified 2021-11 · version 1.0.0
Guarantees a vector register length of at least 1024 bits, so LMUL=1 holds 128 byte-sized elements.
Typical use: Code that requires VLEN of at least 1024 bits
Open Zvl1024b in the explorerDependencies
Requires
Requires one of
Instructions
No instruction encodings are listed for this extension in the catalogue.