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As a hardware designer, you can leverage RISC-V’s flexible ISA to create customized, energy-efficient processors tailored to specific application requirements, fostering innovation across different industries.

Designing to RISC-V specifications can be performed using the processes and tools of your choice. Suggestions for the common design steps are shown below.

1. Prepare​

  1. Become a Member to unlock access to and collaborate with RISC-V experts and complete the “New Member” journey. Because RISC-V is an open ISA standard, this step is optional but should be strongly considered as a way to both contribute to the broader community and get assistance in your journey.
  2. Join the ISA Dev mailing list as a resource for asking questions as they arise. This list is open to non-members.
  3. As a RISC-V member, you may review and engage with these active RISC-V Groups.
  4. Locate relevant reference information:

2. Learn​

Ensuring that you are ready to begin your RISC-V journey begins with education. See the following classesitems to grow your skills.

  1. Enroll in the Free Building a RISC-V CPU Core Course (free)
  2. Computer Architecture with an Industrial RISC-V Core Course (free)
  3. Foundations of RISC-V Assembly Programming Course (free).

3. Locate Resources​

The following resources play a role in RISC-V SOC development:

Existing Cores​

Design Tools​

  • Discover hardware design technologies and tools from our member ecosystem in the RISC-V Landscape.

4. Start Designing​

Integrate the RISC-V resources into your development process to complete your RISC-V design.

5. Verifying your Design​

Verification of RISC-V processors follows industry best practices for processor development. Use the simulator and tests in this section while verifying your work.

Please note, the Architecture Compatibility Tests perform compatibility testing against the standard and provide a valuable supplement to verification tests. These tests do not verify the functional correctness of your product.

ISA Simulators​

  • Golden Model Simulator: The primary simulator written in the formal specification language of Sail. Development of the open source sail-riscv GitHub project is coordinated by the Tech Golden Model group (Members Only). Simulator binaries can be found here.
  • Spike: Another open source RISC-V simulator hosted in the riscv-isa-sim GitHub project.
  • QEMU: The hardware emulation mode of QEMU can be used as a hardware simulator. More information on a RISC-V QEMU can be found here.

ISA Test Suites​

Architecture Compatibility Tests: The RISC-V Architecture Test SIG (members-only group) curates and maintains an open source test suite for testing RISC-V compatibility. See the riscv-arch-test GitHub project. These tests should be run in addition to your full verification suite to ensure RISC-V compatibility.

6. Getting Assistance​

At any point in this process, members and non-members can reach out to RISC-V Staff for assistance.

Open Issues

  1. Other open source cores?
  2. Simulator pointer(s)