mtvec

Machine Trap Vector Control

Controls where traps jump.

Attributes

Requirement

Sm

Defining extensions

Sm

Machine mode

CSR Address

0x305

Length

* 32 when CSR[misa].MXL == 0 * 64 when CSR[misa].MXL == 1

Privilege Mode

M

Format

This CSR format changes dynamically.

mtvec Format when CSR[misa].MXL == 0
Figure 1. mtvec Format when CSR[misa].MXL == 0
mtvec Format when CSR[misa].MXL == 1
Figure 2. mtvec Format when CSR[misa].MXL == 1

Field Summary

Name Location Type Reset Value

mtvec.BASE

* 31:2 when CSR[misa].MXL == 0 * 63:2 when CSR[misa].MXL == 1

[when,"MTVEC_ACCESS == "ro""] RO

[when,"MTVEC_ACCESS != "ro""] RW-R

0

mtvec.MODE

1:0

[when,"(MTVEC_ACCESS == "ro")"] RO [when,"(MTVEC_ACCESS != "ro")"]

[when,"$array_size(MTVEC_MODES) == 1"] RO

[when,"$array_size(MTVEC_MODES) != 1"] RW-R

UNDEFINED_LEGAL

Fields

BASE

Location

  • 31:2 when CSR[misa].MXL == 0

  • 63:2 when CSR[misa].MXL == 1

Description

Bits [MXLEN-1:2] of the exception vector physical address for any trap taken in M-mode.

The implementation physical memory map may resitrict which values are legal in this field.

Type

RO

RW-R

Reset value

0

MODE

Location

1:0

Description

Vectoring mode for asynchronous interrupts.

0 - Direct, 1 - Vectored

When Direct, all synchronous exceptions and asynchronous interrupts jump to (mtvec.BASE << 2).

When Vectored, asynchronous interrupts jump to (mtvec.BASE << 2 + mcause*4) while synchronous exceptions continue to jump to (mtvec.BASE << 2).

Type

RO

RO

RW-R

Reset value

UNDEFINED_LEGAL

Software write

This CSR may store a value that is different from what software attempts to write.

When a software write occurs (e.g., through csrrw), the following determines the written value:

BASE = # Base spec says that BASE must be 4-byte aligned, which will always be the case
# implementations may put further constraints on BASE when MODE != Direct
# If that is the case, stvec should have an override for the implementation

if (csr_value.MODE == 0) {
  if ($array_includes?(MTVEC_MODES, 0)) {
    return csr_value.BASE;
  }
  if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "retain") {
    return CSR[mtvec].BASE;
  }
  if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "custom") {
    return UNDEFINED_LEGAL_DETERMINISTIC;
  }
  unreachable();
} else if (csr_value.MODE == 1) {
  if ($array_includes?(MTVEC_MODES, 1)) {
    return csr_value.BASE;
  }
  if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "retain") {
    return CSR[mtvec].BASE;
  }
  if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "custom") {
    return UNDEFINED_LEGAL_DETERMINISTIC;
  }
  unreachable();
} else {
  if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "retain") {
    return CSR[mtvec].BASE;
  }
  if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "custom") {
    return UNDEFINED_LEGAL_DETERMINISTIC;
  }
  unreachable();
}

MODE = if (csr_value.MODE == 0) {
  if ($array_includes?(MTVEC_MODES, 0)) {
    return csr_value.MODE;
  } else {
    if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "retain") {
      return CSR[mtvec].MODE;
    } else if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "custom") {
      return UNDEFINED_LEGAL_DETERMINISTIC;
    }
  }
} else if (csr_value.MODE == 1) {
  if ($array_includes?(MTVEC_MODES, 1)) {
    return csr_value.MODE;
  } else {
    if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "retain") {
      return CSR[mtvec].MODE;
    } else if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "custom") {
      return UNDEFINED_LEGAL_DETERMINISTIC;
    }
  }
} else {
  if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "retain") {
    return CSR[mtvec].MODE;
  } else if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "custom") {
    return UNDEFINED_LEGAL_DETERMINISTIC;
  }
}
unreachable();