vl

Vector Length

Holds an unsigned integer specifying number of elements to be updated with results from a vector instruction.

Attributes

Requirement

Zvl32b

Defining extensions

Zvl32b

Vector register length must be at least 32 bits

CSR Address

0xc20

Length

* 32 when (priv_mode() == PrivilegeMode::M && CSR[misa].MXL == 0) || (priv_mode() == PrivilegeMode::S && CSR[mstatus].SXL == 0) || (priv_mode() == PrivilegeMode::U && CSR[mstatus].UXL == 0) || (priv_mode() == PrivilegeMode::VS && CSR[hstatus].VSXL == 0) || (priv_mode() == PrivilegeMode::VU && CSR[vsstatus].UXL == 0) * 64 when (priv_mode() == PrivilegeMode::M && CSR[misa].MXL == 1) || (priv_mode() == PrivilegeMode::S && CSR[mstatus].SXL == 1) || (priv_mode() == PrivilegeMode::U && CSR[mstatus].UXL == 1) || (priv_mode() == PrivilegeMode::VS && CSR[hstatus].VSXL == 1) || (priv_mode() == PrivilegeMode::VU && CSR[vsstatus].UXL == 1)

Privilege Mode

U

Format

This CSR format changes dynamically.

vl Format when (priv_mode() == PrivilegeMode::M && CSR[misa].MXL == 0) || (priv_mode() == PrivilegeMode::S && CSR[mstatus].SXL == 0) || (priv_mode() == PrivilegeMode::U && CSR[mstatus].UXL == 0) || (priv_mode() == PrivilegeMode::VS && CSR[hstatus].VSXL == 0) || (priv_mode() == PrivilegeMode::VU && CSR[vsstatus].UXL == 0)
Figure 1. vl Format when (priv_mode() == PrivilegeMode::M && CSR[misa].MXL == 0) || (priv_mode() == PrivilegeMode::S && CSR[mstatus].SXL == 0) || (priv_mode() == PrivilegeMode::U && CSR[mstatus].UXL == 0) || (priv_mode() == PrivilegeMode::VS && CSR[hstatus].VSXL == 0) || (priv_mode() == PrivilegeMode::VU && CSR[vsstatus].UXL == 0)
vl Format when (priv_mode() == PrivilegeMode::M && CSR[misa].MXL == 1) || (priv_mode() == PrivilegeMode::S && CSR[mstatus].SXL == 1) || (priv_mode() == PrivilegeMode::U && CSR[mstatus].UXL == 1) || (priv_mode() == PrivilegeMode::VS && CSR[hstatus].VSXL == 1) || (priv_mode() == PrivilegeMode::VU && CSR[vsstatus].UXL == 1)
Figure 2. vl Format when (priv_mode() == PrivilegeMode::M && CSR[misa].MXL == 1) || (priv_mode() == PrivilegeMode::S && CSR[mstatus].SXL == 1) || (priv_mode() == PrivilegeMode::U && CSR[mstatus].UXL == 1) || (priv_mode() == PrivilegeMode::VS && CSR[hstatus].VSXL == 1) || (priv_mode() == PrivilegeMode::VU && CSR[vsstatus].UXL == 1)

Field Summary

Name Location Type Reset Value

vl.VALUE

* 31:0 when CSR[mstatus].UXL == 0 * 63:0 when CSR[mstatus].UXL == 1

RO-H

UNDEFINED_LEGAL

Fields

VALUE

Location

  • 31:0 when CSR[mstatus].UXL == 0

  • 63:0 when CSR[mstatus].UXL == 1

Description

The vl register holds an unsigned integer specifying the number of elements to be updated with results from a vector instruction, as further detailed in Section Section 31.5.4.

The number of bits implemented in vl depends on the implementation’s maximum vector length of the smallest supported type. The smallest vector implementation with VLEN=32 and supporting SEW=8 would need at least six bits in vl to hold the values 0-32 (VLEN=32, with LMUL=8 and SEW=8, yields VLMAX=32).
Type

RO-H

Reset value

UNDEFINED_LEGAL