Architectural Parameters

The following 147 parameters are defined in this manual:

Name Type Existence Additional Requirements Description

ASID_WIDTH

0 to 16

(MXLEN == 32 → ASID_WIDTH ⇐ 9)

Number of implemented ASID bits. Maximum is 16 for XLEN==64, and 9 for XLEN==32

CACHE_BLOCK_SIZE

[1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536, 131072, 262144, 524288, 1048576, 2097152, 4194304, 8388608, 16777216, 33554432, 67108864, 134217728, 268435456, 536870912, 1073741824, 2147483648, 4294967296, 8589934592, 17179869184, 34359738368, 68719476736, 137438953472, 274877906944, 549755813888, 1099511627776, 2199023255552, 4398046511104, 8796093022208, 17592186044416, 35184372088832, 70368744177664, 140737488355328, 281474976710656, 562949953421312, 1125899906842624, 2251799813685248, 4503599627370496, 9007199254740992, 18014398509481984, 36028797018963968, 72057594037927936, 144115188075855872, 288230376151711744, 576460752303423488, 1152921504606846976, 2305843009213693952, 4611686018427387904, 9223372036854775808]

(Zicbom pass:[

] Zicbop pass:[

] Zicboz)a

None

The observable size of a cache block, in bytes. A cache block is a naturally aligned power-of-two (NAPOT) range of memory.

CACHE_BLOCK_SIZE

(Zicbom pass:[

] Zicbop pass:[

] Zicboz)a

None

The observable size of a cache block, in bytes. A cache block is a naturally aligned power-of-two (NAPOT) range of memory.

CACHE_BLOCK_SIZE

(Zicbom pass:[

] Zicbop pass:[

] Zicboz)a

None

The observable size of a cache block, in bytes. A cache block is a naturally aligned power-of-two (NAPOT) range of memory.

ELEN

[8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536, 131072, 262144, 524288, 1048576, 2097152]

Zvl32ba

None

The maximum size in bits of a vector element that any operation can produce or consume.

FOLLOW_VTYPE_RESET_RECOMMENDATION

boolean

Zvl32ba

None

It is recommended that at reset, vtype.vill is set, the remaining bits in vtype are zero, and vl is set to zero. If this parameter is set to true, this recommendation is followed. If it is false, at reset the respective fields will be UNDEFINED_LEGAL.

FORCE_UPGRADE_CBO_INVAL_TO_FLUSH

boolean

Zicboma

None

When true, an implementation prohibits setting menvcfg.CBIE == 11 such that all cbo.inval instructions either trap (when menvcfg.CBIE == '00') or flush (when menvcfg.CBIE == '01').

When false, an implementation allows a true INVAL operation for cbo.inval, and thus supports the setting menvcfg.CBIE == 11.

GSTAGE_MODE_BARE

boolean

(((32 in SXLEN && SV32X4_TRANSLATION != true) → GSTAGE_MODE_BARE == true) && ((((64 in SXLEN && SV39X4_TRANSLATION != true) && SV48X4_TRANSLATION != true) && SV57X4_TRANSLATION != true) → GSTAGE_MODE_BARE == true))

Whether or not writing mode=Bare is supported in the hgatp register.

HCOUNTENABLE_EN

32-element array of boolean

(((!Zicntr → HCOUNTENABLE_EN[0] != true) && (!Zicntr → HCOUNTENABLE_EN[1] != true) && (!Zicntr → HCOUNTENABLE_EN[2] != true)) && ((!Zihpm → HCOUNTENABLE_EN[3] != true) && (HPM_COUNTER_EN[3] != true → HCOUNTENABLE_EN[3] != true) && (!Zihpm → HCOUNTENABLE_EN[4] != true) && (HPM_COUNTER_EN[4] != true → HCOUNTENABLE_EN[4] != true) && (!Zihpm → HCOUNTENABLE_EN[5] != true) && (HPM_COUNTER_EN[5] != true → HCOUNTENABLE_EN[5] != true) && (!Zihpm → HCOUNTENABLE_EN[6] != true) && (HPM_COUNTER_EN[6] != true → HCOUNTENABLE_EN[6] != true) && (!Zihpm → HCOUNTENABLE_EN[7] != true) && (HPM_COUNTER_EN[7] != true → HCOUNTENABLE_EN[7] != true) && (!Zihpm → HCOUNTENABLE_EN[8] != true) && (HPM_COUNTER_EN[8] != true → HCOUNTENABLE_EN[8] != true) && (!Zihpm → HCOUNTENABLE_EN[9] != true) && (HPM_COUNTER_EN[9] != true → HCOUNTENABLE_EN[9] != true) && (!Zihpm → HCOUNTENABLE_EN[10] != true) && (HPM_COUNTER_EN[10] != true → HCOUNTENABLE_EN[10] != true) && (!Zihpm → HCOUNTENABLE_EN[11] != true) && (HPM_COUNTER_EN[11] != true → HCOUNTENABLE_EN[11] != true) && (!Zihpm → HCOUNTENABLE_EN[12] != true) && (HPM_COUNTER_EN[12] != true → HCOUNTENABLE_EN[12] != true) && (!Zihpm → HCOUNTENABLE_EN[13] != true) && (HPM_COUNTER_EN[13] != true → HCOUNTENABLE_EN[13] != true) && (!Zihpm → HCOUNTENABLE_EN[14] != true) && (HPM_COUNTER_EN[14] != true → HCOUNTENABLE_EN[14] != true) && (!Zihpm → HCOUNTENABLE_EN[15] != true) && (HPM_COUNTER_EN[15] != true → HCOUNTENABLE_EN[15] != true) && (!Zihpm → HCOUNTENABLE_EN[16] != true) && (HPM_COUNTER_EN[16] != true → HCOUNTENABLE_EN[16] != true) && (!Zihpm → HCOUNTENABLE_EN[17] != true) && (HPM_COUNTER_EN[17] != true → HCOUNTENABLE_EN[17] != true) && (!Zihpm → HCOUNTENABLE_EN[18] != true) && (HPM_COUNTER_EN[18] != true → HCOUNTENABLE_EN[18] != true) && (!Zihpm → HCOUNTENABLE_EN[19] != true) && (HPM_COUNTER_EN[19] != true → HCOUNTENABLE_EN[19] != true) && (!Zihpm → HCOUNTENABLE_EN[20] != true) && (HPM_COUNTER_EN[20] != true → HCOUNTENABLE_EN[20] != true) && (!Zihpm → HCOUNTENABLE_EN[21] != true) && (HPM_COUNTER_EN[21] != true → HCOUNTENABLE_EN[21] != true) && (!Zihpm → HCOUNTENABLE_EN[22] != true) && (HPM_COUNTER_EN[22] != true → HCOUNTENABLE_EN[22] != true) && (!Zihpm → HCOUNTENABLE_EN[23] != true) && (HPM_COUNTER_EN[23] != true → HCOUNTENABLE_EN[23] != true) && (!Zihpm → HCOUNTENABLE_EN[24] != true) && (HPM_COUNTER_EN[24] != true → HCOUNTENABLE_EN[24] != true) && (!Zihpm → HCOUNTENABLE_EN[25] != true) && (HPM_COUNTER_EN[25] != true → HCOUNTENABLE_EN[25] != true) && (!Zihpm → HCOUNTENABLE_EN[26] != true) && (HPM_COUNTER_EN[26] != true → HCOUNTENABLE_EN[26] != true) && (!Zihpm → HCOUNTENABLE_EN[27] != true) && (HPM_COUNTER_EN[27] != true → HCOUNTENABLE_EN[27] != true) && (!Zihpm → HCOUNTENABLE_EN[28] != true) && (HPM_COUNTER_EN[28] != true → HCOUNTENABLE_EN[28] != true) && (!Zihpm → HCOUNTENABLE_EN[29] != true) && (HPM_COUNTER_EN[29] != true → HCOUNTENABLE_EN[29] != true) && (!Zihpm → HCOUNTENABLE_EN[30] != true) && (HPM_COUNTER_EN[30] != true → HCOUNTENABLE_EN[30] != true) && (!Zihpm → HCOUNTENABLE_EN[31] != true) && (HPM_COUNTER_EN[31] != true → HCOUNTENABLE_EN[31] != true)))

Indicates which counters can delegated via hcounteren

An unimplemented counter cannot be specified, i.e., if HPM_COUNTER_EN[3] is false, it would be illegal to set HCOUNTENABLE_EN[3] to true.

HCOUNTENABLE_EN[0:2] must all be false if Zicntr is not implemented. HCOUNTENABLE_EN[3:31] must all be false if Zihpm is not implemented.

HPM_COUNTER_EN

32-element array where:
  [0] is false
  [1] is false
  [2] is false
additional items are:
  boolean

Sma

None

Whether each HPM counter is implemented in hardware.

HPM_COUNTER_EN[n] being false means hpmcounter<n>/mhpmcounter<n> and the corresponding mhpmevent<n> are not implemented and are hardwired read-only zero. (It does not mean the counter is implemented but currently stopped from counting; that is a separate, run-time concept controlled by mcountinhibit.)

There is one entry for each hpmcounter, indexed 0-31.

Indices 0-2 must be false: they are placeholders for the three counters (cycle/mcycle (CY), time ™, and instret/minstret (IR)) whose implementation this parameter does not control. These counters are associated with indexes 0, 1, and 2. The rest of the HPM counters logically follow at indexes 3-31. Index 3 in HPM_COUNTER_EN corresponds to mhpmcounter3. Index 31 in HPM_COUNTER_EN corresponds to mhpmcounter31.

IGNORE_INVALID_VSATP_MODE_WRITES_WHEN_V_EQ_ZERO

boolean

None

Whether writes from M-mode, U-mode, or S-mode to vsatp with an illegal mode setting are ignored (as they are with satp), or if they are treated as WARL, leading to undpredictable behavior.

IMPRECISE_VECTOR_TRAP_SETTABLE

boolean

Zvl32ba

None

Some profiles may provide a privileged configuration bit that selects between precise and imprecise vector trap behavior, allowing flexibility in how traps and partial updates are reported.

JVT_BASE_TYPE

[mask, custom]

Zcmta

None

Type of the jvt.BASE CSR field. One of:

mask: jvt.BASE contains one or more implemented bits, which are indicated by JVT_BASE_MASK.
custom: Custom behavior. Will cause hart to enter 'unpredictable' state on a write to jvt.BASE.

JVT_READ_ONLY

boolean

Zcmta

None

If Zcmt is implemented, JVT is implemented, but can contain a read-only value

LEGAL_VSTART

[1_stride, 2_stride, 4_stride, custom]

Zvl32ba

None

Implementations may raise illegal-instruction exceptions for vector instructions that specify a vstart value the implementation can never produce under the same vtype configuration (e.g., due to restrictions on supported strides or alignments).

MARCHID_IMPLEMENTED

boolean

Sma

None

false: marchid is not implemented, and must be read-only-0
true: marchid is implemented, and the value is determined by ARCH_ID_VALUE

MCOUNTENABLE_EN

32-element array of boolean

Sma

(((!Zicntr → MCOUNTENABLE_EN[0] != true) && (!Zicntr → MCOUNTENABLE_EN[1] != true) && (!Zicntr → MCOUNTENABLE_EN[2] != true)) && ((!Zihpm → MCOUNTENABLE_EN[3] != true) && (MCOUNTENABLE_EN[3] == true → HPM_COUNTER_EN[3] == true) && (!Zihpm → MCOUNTENABLE_EN[4] != true) && (MCOUNTENABLE_EN[4] == true → HPM_COUNTER_EN[4] == true) && (!Zihpm → MCOUNTENABLE_EN[5] != true) && (MCOUNTENABLE_EN[5] == true → HPM_COUNTER_EN[5] == true) && (!Zihpm → MCOUNTENABLE_EN[6] != true) && (MCOUNTENABLE_EN[6] == true → HPM_COUNTER_EN[6] == true) && (!Zihpm → MCOUNTENABLE_EN[7] != true) && (MCOUNTENABLE_EN[7] == true → HPM_COUNTER_EN[7] == true) && (!Zihpm → MCOUNTENABLE_EN[8] != true) && (MCOUNTENABLE_EN[8] == true → HPM_COUNTER_EN[8] == true) && (!Zihpm → MCOUNTENABLE_EN[9] != true) && (MCOUNTENABLE_EN[9] == true → HPM_COUNTER_EN[9] == true) && (!Zihpm → MCOUNTENABLE_EN[10] != true) && (MCOUNTENABLE_EN[10] == true → HPM_COUNTER_EN[10] == true) && (!Zihpm → MCOUNTENABLE_EN[11] != true) && (MCOUNTENABLE_EN[11] == true → HPM_COUNTER_EN[11] == true) && (!Zihpm → MCOUNTENABLE_EN[12] != true) && (MCOUNTENABLE_EN[12] == true → HPM_COUNTER_EN[12] == true) && (!Zihpm → MCOUNTENABLE_EN[13] != true) && (MCOUNTENABLE_EN[13] == true → HPM_COUNTER_EN[13] == true) && (!Zihpm → MCOUNTENABLE_EN[14] != true) && (MCOUNTENABLE_EN[14] == true → HPM_COUNTER_EN[14] == true) && (!Zihpm → MCOUNTENABLE_EN[15] != true) && (MCOUNTENABLE_EN[15] == true → HPM_COUNTER_EN[15] == true) && (!Zihpm → MCOUNTENABLE_EN[16] != true) && (MCOUNTENABLE_EN[16] == true → HPM_COUNTER_EN[16] == true) && (!Zihpm → MCOUNTENABLE_EN[17] != true) && (MCOUNTENABLE_EN[17] == true → HPM_COUNTER_EN[17] == true) && (!Zihpm → MCOUNTENABLE_EN[18] != true) && (MCOUNTENABLE_EN[18] == true → HPM_COUNTER_EN[18] == true) && (!Zihpm → MCOUNTENABLE_EN[19] != true) && (MCOUNTENABLE_EN[19] == true → HPM_COUNTER_EN[19] == true) && (!Zihpm → MCOUNTENABLE_EN[20] != true) && (MCOUNTENABLE_EN[20] == true → HPM_COUNTER_EN[20] == true) && (!Zihpm → MCOUNTENABLE_EN[21] != true) && (MCOUNTENABLE_EN[21] == true → HPM_COUNTER_EN[21] == true) && (!Zihpm → MCOUNTENABLE_EN[22] != true) && (MCOUNTENABLE_EN[22] == true → HPM_COUNTER_EN[22] == true) && (!Zihpm → MCOUNTENABLE_EN[23] != true) && (MCOUNTENABLE_EN[23] == true → HPM_COUNTER_EN[23] == true) && (!Zihpm → MCOUNTENABLE_EN[24] != true) && (MCOUNTENABLE_EN[24] == true → HPM_COUNTER_EN[24] == true) && (!Zihpm → MCOUNTENABLE_EN[25] != true) && (MCOUNTENABLE_EN[25] == true → HPM_COUNTER_EN[25] == true) && (!Zihpm → MCOUNTENABLE_EN[26] != true) && (MCOUNTENABLE_EN[26] == true → HPM_COUNTER_EN[26] == true) && (!Zihpm → MCOUNTENABLE_EN[27] != true) && (MCOUNTENABLE_EN[27] == true → HPM_COUNTER_EN[27] == true) && (!Zihpm → MCOUNTENABLE_EN[28] != true) && (MCOUNTENABLE_EN[28] == true → HPM_COUNTER_EN[28] == true) && (!Zihpm → MCOUNTENABLE_EN[29] != true) && (MCOUNTENABLE_EN[29] == true → HPM_COUNTER_EN[29] == true) && (!Zihpm → MCOUNTENABLE_EN[30] != true) && (MCOUNTENABLE_EN[30] == true → HPM_COUNTER_EN[30] == true) && (!Zihpm → MCOUNTENABLE_EN[31] != true) && (MCOUNTENABLE_EN[31] == true → HPM_COUNTER_EN[31] == true)))

Indicates which counters can be delegated via mcounteren.

An unimplemented counter cannot be specified, i.e., if HPM_COUNTER_EN[3] is false, it would be illegal to set MCOUNTENABLE_EN[3] to true.

MCOUNTENABLE_EN[0:2] must all be false if Zicntr is not implemented. MCOUNTENABLE_EN[3:31] must all be false if Zihpm is not implemented.

MCOUNTINHIBIT_IMPLEMENTED

boolean

Sma

None

Options:

true: The mcountinhibit CSR is implemented and can be accessed in M-mode.
false: The mcountinhibit CSR is not implemented. Accessing the CSR will cause an IllegalInstruction trap or enter an unpredictable state, depending on TRAP_ON_UNIMPLEMENTED_CSR.

MIMPID_IMPLEMENTED

boolean

Sma

None

false: mimpid is not implemented, and must be read-only-0
true: mimpid is implemented, and the value is determined by IMP_ID_VALUE

MISALIGNED_LDST

boolean

Sma

None

Does the implementation perform non-atomic misaligned loads and stores to main memory (does not affect misaligned support to device memory)? If not, the implementation always throws a misaligned exception.

MISALIGNED_LDST_EXCEPTION_PRIORITY

[low, high]

Sma

(MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE > 1 → MISALIGNED_LDST_EXCEPTION_PRIORITY == low)

The relative priority of a load/store/AMO exception vs. load/store/AMO page-fault or access-fault exceptions.

May be one of:

low

Misaligned load/store/AMO exceptions are always lower priority than load/store/AMO page-fault and access-fault exceptions.

high

Misaligned load/store/AMO exceptions are always higher priority than load/store/AMO page-fault and access-fault exceptions.

MISALIGNED_LDST_EXCEPTION_PRIORITY cannot be "high" when MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE is non-zero, since the atomicity of an access cannot be determined in that case until after address translation.

MISA_CSR_IMPLEMENTED

boolean

Sma

None

Options:

true: The misa CSR returns a non-zero value.
false: The misa CSR is read-only-0.

MSTATUS_FS_LEGAL_VALUES

1-element to 4-element array of [0, 1, 2, 3]

(Sm && (F pass:[

] S))a

((F && (HW_MSTATUS_FS_DIRTY_UPDATE == precise pass:[

] HW_MSTATUS_FS_DIRTY_UPDATE == imprecise)) → 3 in MSTATUS_FS_LEGAL_VALUES)

The set of values that mstatus.FS supports.

MSTATUS_VS_LEGAL_VALUES

1-element to 4-element array of [0, 1, 2, 3]

(Sm && (Zvl32b pass:[

] S))a

((V → MSTATUS_VS_LEGAL_VALUES > 1) && ((V && (HW_MSTATUS_VS_DIRTY_UPDATE == precise pass:[

] HW_MSTATUS_VS_DIRTY_UPDATE == imprecise)) → (0 in MSTATUS_VS_LEGAL_VALUES && 3 in MSTATUS_VS_LEGAL_VALUES)))

The set of values that mstatus.VS will accept from a software write.

MTVAL_WIDTH

0 to 64

Sma

((MXLEN == 32 → MTVAL_WIDTH ⇐ 32) && (((MXLEN == 32 && PHYS_ADDR_WIDTH > 32) && ((((((((Sdext pass:[

] REPORT_VA_IN_MTVAL_ON_BREAKPOINT == true) pass:[

] REPORT_ENCODING_IN_MTVAL_ON_ILLEGAL_INSTRUCTION == true) pass:[

] REPORT_VA_IN_MTVAL_ON_LOAD_MISALIGNED == true) pass:[

] REPORT_VA_IN_MTVAL_ON_STORE_AMO_MISALIGNED == true) pass:[

] REPORT_VA_IN_MTVAL_ON_INSTRUCTION_MISALIGNED == true) pass:[

] REPORT_VA_IN_MTVAL_ON_LOAD_ACCESS_FAULT == true) pass:[

] REPORT_VA_IN_MTVAL_ON_STORE_AMO_ACCESS_FAULT == true) pass:[

] REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT == true)) → MTVAL_WIDTH == 32) && (REPORT_ENCODING_IN_MTVAL_ON_ILLEGAL_INSTRUCTION == true → MTVAL_WIDTH >= 32))

The number of implemented bits in the mtval CSR. This is the CSR that may be written when a trap is taken into M-mode with exception-specific information to assist software in handling the trap (e.g., address associated with exception).

Must be greater than or equal to max(PHYS_ADDR_WIDTH, VA_SIZE)

MTVEC_ACCESS

[ro, rw]

Sma

None

Options:

ro: mtvec is read-only.
rw: mtvec is read-write, but may not accept all values.

MTVEC_ILLEGAL_WRITE_BEHAVIOR

[retain, custom]

Sma

None

Options:

retain: When either mtvec.MODE or mtvec.BASE is illegal, mtvec will retain its current value
custom: When either mtvec.MODE or mtvec.BASE is illegal, mtvec will obtain an unpredictable value

Other values may be added over time once other common behaviors are identified.

MTVEC_MODES

1-element to 2-element array of [0, 1]

Sma

(MTVEC_ACCESS == ro → MTVEC_MODES == 1)

Options:

0: Direct; All traps set pc to mtvec.BASE
1: Vectored; Asynchronous interrupts set pc to mtvec.BASE + 4 x cause.

If only one mode is given, mtvec.MODE is assumed to be read-only with that value. Otherwise, mtvec.MODE is read-write.

MUTABLE_MISA_H

boolean

(Sm && H)a

(MUTABLE_MISA_S == true → MUTABLE_MISA_H == true)

Indicates whether or not the H extension can be disabled with the misa.H bit.

MUTABLE_MISA_S

boolean

(S && Sm)a

(MUTABLE_MISA_U == true → MUTABLE_MISA_S == true)

Indicates whether or not the S extension can be disabled with the misa.S bit.

MXLEN

[32, 64]

Sma

((MXLEN == 32 → xlen() == 32) && (xlen() == 64 → MXLEN == 64) && ((MXLEN == 64 && !U) → xlen() == 64) && ((((((MXLEN == 64 && H) && !32 in VUXLEN) && !32 in VSXLEN) && !32 in UXLEN) && !32 in SXLEN) → xlen() == 64) && (((((MXLEN == 64 && S) && !H) && !32 in UXLEN) && !32 in SXLEN) → xlen() == 64) && (((((MXLEN == 64 && U) && !S) && !H) && !32 in UXLEN) → xlen() == 64))

XLEN in machine mode, specified in bits

M_MODE_ENDIANNESS

[little, big, dynamic]

Sma

None

Options:

little

M-mode data is always little endian

big

M-mode data is always big endian

dynamic

M-mode data can be either little or big endian, depending on the CSR field mstatus.MBE

NUM_EXTERNAL_GUEST_INTERRUPTS

1 to 63

(MXLEN == 32 → NUM_EXTERNAL_GUEST_INTERRUPTS ⇐ 31)

Number of supported virtualized guest interrupts

Corresponds to the GEILEN parameter in the RVI specs

NUM_PMP_ENTRIES

[0, 16, 64]

Sma

None

Number of implemented PMP entries.

The architecture mandates that the number of implemented PMP registers must appear to be 0, 16, or 64, so NUM_PMP_ENTRIES must be one of those values. It directly determines which PMP registers exist: pmpaddr0-pmpaddr<N-1> and their corresponding pmpNcfg fields are implemented, and the rest are not. Accessing an unimplemented PMP register causes an IllegalInstruction when TRAP_ON_UNIMPLEMENTED_CSR is true.

pmpcfgN for an odd N never exists when XLEN == 64.

An implemented entry may still be read-only zero (but will never cause an exception). The number of entries that are actually usable is given by NUM_USABLE_PMP_ENTRIES.

PHYS_ADDR_WIDTH

1 to 64

Sma

((MXLEN == 32 → PHYS_ADDR_WIDTH ⇐ 34) && ((MXLEN == 32 && !Sv32) → PHYS_ADDR_WIDTH ⇐ 32))

Implementation-defined size of the physical address space.

PMA_GRANULARITY

2 to 66

Sma

None

Generally, for systems with an MMU, should not be smaller than 12, as that would preclude caching PMA results in the TLB along with virtual memory translations

PRECISE_SYNCHRONOUS_EXCEPTIONS

boolean

Sma

None

If false, any exception not otherwise mandated to precise (e.g., PMP violation) will cause execution to enter an unpredictable state.

REPORT_CAUSE_IN_MTVAL_ON_LANDING_PAD_SOFTWARE_CHECK

boolean

Zicfilpa

None

When true, mtval is written with the shadow stack cause (code=18) when a SoftwareCheck exception is raised into M-mode due to a landing pad error.

When false, mtval is written with 0.

REPORT_CAUSE_IN_MTVAL_ON_SHADOW_STACK_SOFTWARE_CHECK

boolean

Zicfissa

None

When true, mtval is written with the shadow stack cause (code=3) when a SoftwareCheck exception is raised into M-mode due to a shadow stack pop check instruction.

When false, mtval is written with 0.

REPORT_CAUSE_IN_STVAL_ON_LANDING_PAD_SOFTWARE_CHECK

boolean

Zicfilpa

None

When true, stval is written with the shadow stack cause (code=18) when a SoftwareCheck exception is raised into S-mode due to a landing pad error.

When false, stval is written with 0.

REPORT_CAUSE_IN_STVAL_ON_SHADOW_STACK_SOFTWARE_CHECK

boolean

Zicfissa

None

When true, stval is written with the shadow stack cause (code=3) when a SoftwareCheck exception is raised into S-mode due to a shadow stack pop check instruction.

When false, stval is written with 0.

REPORT_CAUSE_IN_VSTVAL_ON_LANDING_PAD_SOFTWARE_CHECK

boolean

Zicfilpa

None

When true, vstval is written with the shadow stack cause (code=18) when a SoftwareCheck exception is raised into VS-mode due to a landing pad error.

When false, vstval is written with 0.

REPORT_CAUSE_IN_VSTVAL_ON_SHADOW_STACK_SOFTWARE_CHECK

boolean

Zicfissa

None

When true, vstval is written with the shadow stack cause (code=3) when a SoftwareCheck exception is raised into VS-mode due to a shadow stack pop check instruction.

When false, vstval is written with 0.

REPORT_ENCODING_IN_MTVAL_ON_ILLEGAL_INSTRUCTION

boolean

Sma

None

Options:

true: mtval is written with the encoding of an instruction causing an IllegalInstruction exception
false: mtval is written with 0 when an instruction causes an IllegalInstruction exception.

REPORT_ENCODING_IN_STVAL_ON_ILLEGAL_INSTRUCTION

boolean

None

When true, stval is written with the encoding of an instruction that causes an IllegalInstruction exception.

When false stval is written with 0 when an IllegalInstruction exception occurs.

REPORT_ENCODING_IN_VSTVAL_ON_ILLEGAL_INSTRUCTION

boolean

None

When true, vstval is written with the encoding of an instruction that causes an IllegalInstruction exception.

When false vstval is written with 0 when an IllegalInstruction exception occurs.

REPORT_ENCODING_IN_VSTVAL_ON_VIRTUAL_INSTRUCTION

boolean

None

When true, vstval is written with the encoding of an instruction that causes an VirualInstruction exception.

When false vstval is written with 0 when an VirtualInstruction exception occurs.

REPORT_GPA_IN_HTVAL_ON_GUEST_PAGE_FAULT

boolean

None

When true, htval is written with the Guest Physical Address, shifted right by 2, that caused a GuestPageFault exception.

When false, htval is written with 0 when a GuestPageFault exception occurs.

REPORT_GPA_IN_TVAL_ON_INSTRUCTION_GUEST_PAGE_FAULT

boolean

None

Whether or not GPA >> 2 is written into htval/mtval2 when an instruction guest page fault occurs.

If false, 0 will be written into htval/mtval2 on an instruction guest page fault.

REPORT_GPA_IN_TVAL_ON_INTERMEDIATE_GUEST_PAGE_FAULT

boolean

None

Whether or not GPA >> 2 is written into htval/mtval2 when a guest page fault occurs while walking a VS-mode page table.

If false, 0 will be written into htval/mtval2 on an intermediate guest page fault.

REPORT_GPA_IN_TVAL_ON_LOAD_GUEST_PAGE_FAULT

boolean

None

Whether or not GPA >> 2 is written into htval/mtval2 when a load guest page fault occurs.

If false, 0 will be written into htval/mtval2 on a load guest page fault.

REPORT_GPA_IN_TVAL_ON_STORE_AMO_GUEST_PAGE_FAULT

boolean

None

Whether or not GPA >> 2 is written into htval/mtval2 when a store/amo guest page fault occurs.

If false, 0 will be written into htval/mtval2 on a store/amo guest page fault.

REPORT_VA_IN_MTVAL_ON_BREAKPOINT

boolean

Sma

None

Options:

true: mtval is written with the virtual PC of an EBREAK instruction (same information as mepc).
false: mtval is written with 0 on an EBREAK instruction.

Regardless, mtval is always written with a virtual PC when an external breakpoint is generated

REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT

boolean

Sma

None

Options:

true: mtval is written with the virtual address of a fetch causing the access fault
false: mtval is written with 0 when a fetch causes an access fault

REPORT_VA_IN_MTVAL_ON_INSTRUCTION_MISALIGNED

boolean

Sma

None

Options:

true: mtval is written with the virtual address of a trapping misaligned fetch
false: mtval is written with 0 when a misaligned fetch traps

REPORT_VA_IN_MTVAL_ON_INSTRUCTION_PAGE_FAULT

boolean

None

When true, mtval is written with the virtual PC of an instructino when fetch causes an InstructionPageFault.

WHen false, mtval is written with 0 when an instruction fetch causes an InstructionPageFault.

REPORT_VA_IN_MTVAL_ON_LOAD_ACCESS_FAULT

boolean

Sma

None

Options:

true: mtval is written with the virtual address of a load causing the access fault
false: mtval is written with 0 when a load causes an access fault

REPORT_VA_IN_MTVAL_ON_LOAD_MISALIGNED

boolean

Sma

None

Options:

true: mtval is written with the virtual address of a trapping misaligned load.
false: mtval is written with 0 when a misaligned load traps.

REPORT_VA_IN_MTVAL_ON_LOAD_PAGE_FAULT

boolean

None

When true, mtval is written with the virtual address of a load when it causes a LoadPageFault.

WHen false, mtval is written with 0 when a load causes a LoadPageFault.

REPORT_VA_IN_MTVAL_ON_STORE_AMO_ACCESS_FAULT

boolean

Sma

None

Options:

true: mtval is written with the virtual address of a store or AMO causing the access fault
false: mtval is written with 0 when a store or AMO causes an access fault

REPORT_VA_IN_MTVAL_ON_STORE_AMO_MISALIGNED

boolean

Sma

None

Options:

true: mtval is written with the virtual address of a trapping misaligned store or AMO.
false: mtval is written with 0 when a misaligned store or AMO traps.

REPORT_VA_IN_MTVAL_ON_STORE_AMO_PAGE_FAULT

boolean

None

When true, mtval is written with the virtual address of a store when it causes a StoreAmoPageFault.

WHen false, mtval is written with 0 when a store causes a StoreAmoPageFault.

REPORT_VA_IN_STVAL_ON_BREAKPOINT

boolean

None

When true, stval is written with the virtual PC of the EBREAK instruction (same information as mepc).

When false, stval is written with 0 on an EBREAK instruction.

Regardless, stval is always written with a virtual PC when an external breakpoint is generated

REPORT_VA_IN_STVAL_ON_INSTRUCTION_ACCESS_FAULT

boolean

None

When true, stval is written with the virtual PC of an instructino when fetch causes an InstructionAccessFault.

WHen false, stval is written with 0 when an instruction fetch causes an InstructionAccessFault.

REPORT_VA_IN_STVAL_ON_INSTRUCTION_MISALIGNED

boolean

None

When true, stval is written with the virtual PC when an instruction fetch is misaligned.

When false, stval is written with 0 when an instruction fetch is misaligned.

Note that when IALIGN=16 (i.e., when the C or one of the Zc* extensions are implemented), it is impossible to generate a misaligned fetch, and so this parameter has no effect.

REPORT_VA_IN_STVAL_ON_INSTRUCTION_PAGE_FAULT

boolean

None

When true, stval is written with the virtual PC of an instructino when fetch causes an InstructionPageFault.

WHen false, stval is written with 0 when an instruction fetch causes an InstructionPageFault.

REPORT_VA_IN_STVAL_ON_LOAD_ACCESS_FAULT

boolean

None

When true, stval is written with the virtual address of a load when it causes a LoadAccessFault.

WHen false, stval is written with 0 when a load causes a LoadAccessFault.

REPORT_VA_IN_STVAL_ON_LOAD_MISALIGNED

boolean

None

When true, stval is written with the virtual address of a load instruction when the address is misaligned and MISALIGNED_LDST is false.

When false, stval is written with 0 when a load address is misaligned and MISALIGNED_LDST is false.

REPORT_VA_IN_STVAL_ON_LOAD_PAGE_FAULT

boolean

None

When true, stval is written with the virtual address of a load when it causes a LoadPageFault.

WHen false, stval is written with 0 when a load causes a LoadPageFault.

REPORT_VA_IN_STVAL_ON_STORE_AMO_ACCESS_FAULT

boolean

None

When true, stval is written with the virtual address of a store when it causes a StoreAmoAccessFault.

WHen false, stval is written with 0 when a store causes a StoreAmoAccessFault.

REPORT_VA_IN_STVAL_ON_STORE_AMO_MISALIGNED

boolean

None

When true, stval is written with the virtual address of a store instruction when the address is misaligned and MISALIGNED_LDST is false.

When false, stval is written with 0 when a store address is misaligned and MISALIGNED_LDST is false.

REPORT_VA_IN_STVAL_ON_STORE_AMO_PAGE_FAULT

boolean

None

When true, stval is written with the virtual address of a store when it causes a StoreAmoPageFault.

WHen false, stval is written with 0 when a store causes a StoreAmoPageFault.

REPORT_VA_IN_VSTVAL_ON_BREAKPOINT

boolean

None

When true, vstval is written with the virtual PC of the EBREAK instruction (same information as mepc).

When false, vstval is written with 0 on an EBREAK instruction.

Regardless, vstval is always written with a virtual PC when an external breakpoint is generated.

REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_ACCESS_FAULT

boolean

None

When true, vstval is written with the virtual PC of an instructino when fetch causes an InstructionAccessFault.

WHen false, vstval is written with 0 when an instruction fetch causes an InstructionAccessFault.

REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_MISALIGNED

boolean

None

When true, vstval is written with the virtual PC when an instruction fetch is misaligned.

When false, vstval is written with 0 when an instruction fetch is misaligned.

Note that when IALIGN=16 (i.e., when the C or one of the Zc* extensions are implemented), it is impossible to generate a misaligned fetch, and so this parameter has no effect.

REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_PAGE_FAULT

boolean

None

When true, vstval is written with the virtual PC of an instructino when fetch causes an InstructionPageFault.

WHen false, vstval is written with 0 when an instruction fetch causes an InstructionPageFault.

REPORT_VA_IN_VSTVAL_ON_LOAD_ACCESS_FAULT

boolean

None

When true, vstval is written with the virtual address of a load when it causes a LoadAccessFault.

WHen false, vstval is written with 0 when a load causes a LoadAccessFault.

REPORT_VA_IN_VSTVAL_ON_LOAD_MISALIGNED

boolean

None

When true, vstval is written with the virtual address of a load instruction when the address is misaligned and MISALIGNED_LDST is false.

When false, vstval is written with 0 when a load address is misaligned and MISALIGNED_LDST is false.

REPORT_VA_IN_VSTVAL_ON_LOAD_PAGE_FAULT

boolean

None

When true, vstval is written with the virtual address of a load when it causes a LoadPageFault.

WHen false, vstval is written with 0 when a load causes a LoadPageFault.

REPORT_VA_IN_VSTVAL_ON_STORE_AMO_ACCESS_FAULT

boolean

None

When true, vstval is written with the virtual address of a store when it causes a StoreAmoAccessFault.

WHen false, vstval is written with 0 when a store causes a StoreAmoAccessFault.

REPORT_VA_IN_VSTVAL_ON_STORE_AMO_MISALIGNED

boolean

None

When true, vstval is written with the virtual address of a store instruction when the address is misaligned and MISALIGNED_LDST is false.

When false, vstval is written with 0 when a store address is misaligned and MISALIGNED_LDST is false.

REPORT_VA_IN_VSTVAL_ON_STORE_AMO_PAGE_FAULT

boolean

None

When true, vstval is written with the virtual address of a store when it causes a StoreAmoPageFault.

WHen false, vstval is written with 0 when a store causes a StoreAmoPageFault.

RESERVED_VSET_X0X0_VILL_SET

[never, always, custom]

Zvl32ba

None

When rs1 = x0 and rd = x0, vset instructions act as if the current vector length in vl is used as the AVL. If vill is set or the configuration is reserved, implementations may set vill to indicate unsupported use of these encodings.

RESERVED_VSET_X0X0_VLMAX_CHANGE

[never, always, custom]

Zvl32ba

None

When rs1=x0 and rd=x0, the instructions operate as if the current vector length in vl is used as the AVL. Use of the vset instructions with a new SEW/LMUL ratio that would result in a change of VLMAX is reserved. Implementations may set vill in either case.

RVV_VL_WHEN_AVL_LT_DOUBLE_VLMAX

[ceil(AVL/2), VLMAX, custom]

Zvl32ba

None

The value assigned to VL when AVL < 2*VLMAX.

SATP_MODE_BARE

boolean

None

Whether or not satp.MODE == Bare is supported.

SCOUNTENABLE_EN

32-element array of boolean

(((!Zicntr → SCOUNTENABLE_EN[0] != true) && (!Zicntr → SCOUNTENABLE_EN[1] != true) && (!Zicntr → SCOUNTENABLE_EN[2] != true)) && ((!Zihpm → SCOUNTENABLE_EN[3] != true) && (HPM_COUNTER_EN[3] != true → SCOUNTENABLE_EN[3] != true) && (!Zihpm → SCOUNTENABLE_EN[4] != true) && (HPM_COUNTER_EN[4] != true → SCOUNTENABLE_EN[4] != true) && (!Zihpm → SCOUNTENABLE_EN[5] != true) && (HPM_COUNTER_EN[5] != true → SCOUNTENABLE_EN[5] != true) && (!Zihpm → SCOUNTENABLE_EN[6] != true) && (HPM_COUNTER_EN[6] != true → SCOUNTENABLE_EN[6] != true) && (!Zihpm → SCOUNTENABLE_EN[7] != true) && (HPM_COUNTER_EN[7] != true → SCOUNTENABLE_EN[7] != true) && (!Zihpm → SCOUNTENABLE_EN[8] != true) && (HPM_COUNTER_EN[8] != true → SCOUNTENABLE_EN[8] != true) && (!Zihpm → SCOUNTENABLE_EN[9] != true) && (HPM_COUNTER_EN[9] != true → SCOUNTENABLE_EN[9] != true) && (!Zihpm → SCOUNTENABLE_EN[10] != true) && (HPM_COUNTER_EN[10] != true → SCOUNTENABLE_EN[10] != true) && (!Zihpm → SCOUNTENABLE_EN[11] != true) && (HPM_COUNTER_EN[11] != true → SCOUNTENABLE_EN[11] != true) && (!Zihpm → SCOUNTENABLE_EN[12] != true) && (HPM_COUNTER_EN[12] != true → SCOUNTENABLE_EN[12] != true) && (!Zihpm → SCOUNTENABLE_EN[13] != true) && (HPM_COUNTER_EN[13] != true → SCOUNTENABLE_EN[13] != true) && (!Zihpm → SCOUNTENABLE_EN[14] != true) && (HPM_COUNTER_EN[14] != true → SCOUNTENABLE_EN[14] != true) && (!Zihpm → SCOUNTENABLE_EN[15] != true) && (HPM_COUNTER_EN[15] != true → SCOUNTENABLE_EN[15] != true) && (!Zihpm → SCOUNTENABLE_EN[16] != true) && (HPM_COUNTER_EN[16] != true → SCOUNTENABLE_EN[16] != true) && (!Zihpm → SCOUNTENABLE_EN[17] != true) && (HPM_COUNTER_EN[17] != true → SCOUNTENABLE_EN[17] != true) && (!Zihpm → SCOUNTENABLE_EN[18] != true) && (HPM_COUNTER_EN[18] != true → SCOUNTENABLE_EN[18] != true) && (!Zihpm → SCOUNTENABLE_EN[19] != true) && (HPM_COUNTER_EN[19] != true → SCOUNTENABLE_EN[19] != true) && (!Zihpm → SCOUNTENABLE_EN[20] != true) && (HPM_COUNTER_EN[20] != true → SCOUNTENABLE_EN[20] != true) && (!Zihpm → SCOUNTENABLE_EN[21] != true) && (HPM_COUNTER_EN[21] != true → SCOUNTENABLE_EN[21] != true) && (!Zihpm → SCOUNTENABLE_EN[22] != true) && (HPM_COUNTER_EN[22] != true → SCOUNTENABLE_EN[22] != true) && (!Zihpm → SCOUNTENABLE_EN[23] != true) && (HPM_COUNTER_EN[23] != true → SCOUNTENABLE_EN[23] != true) && (!Zihpm → SCOUNTENABLE_EN[24] != true) && (HPM_COUNTER_EN[24] != true → SCOUNTENABLE_EN[24] != true) && (!Zihpm → SCOUNTENABLE_EN[25] != true) && (HPM_COUNTER_EN[25] != true → SCOUNTENABLE_EN[25] != true) && (!Zihpm → SCOUNTENABLE_EN[26] != true) && (HPM_COUNTER_EN[26] != true → SCOUNTENABLE_EN[26] != true) && (!Zihpm → SCOUNTENABLE_EN[27] != true) && (HPM_COUNTER_EN[27] != true → SCOUNTENABLE_EN[27] != true) && (!Zihpm → SCOUNTENABLE_EN[28] != true) && (HPM_COUNTER_EN[28] != true → SCOUNTENABLE_EN[28] != true) && (!Zihpm → SCOUNTENABLE_EN[29] != true) && (HPM_COUNTER_EN[29] != true → SCOUNTENABLE_EN[29] != true) && (!Zihpm → SCOUNTENABLE_EN[30] != true) && (HPM_COUNTER_EN[30] != true → SCOUNTENABLE_EN[30] != true) && (!Zihpm → SCOUNTENABLE_EN[31] != true) && (HPM_COUNTER_EN[31] != true → SCOUNTENABLE_EN[31] != true)))

Indicates which counters can delegated via scounteren

An unimplemented counter cannot be specified, i.e., if HPM_COUNTER_EN[3] is false, it would be illegal to set SCOUNTENABLE_EN[3] to true.

SCOUNTENABLE_EN[0:2] must all be false if Zicntr is not implemented. SCOUNTENABLE_EN[3:31] must all be false if Zihpm is not implemented.

SEW_MIN

[8, 16, 32, 64]

Zvl32ba

None

Implementations must provide fractional LMUL settings that allow the narrowest supported element width (SEW) to occupy a fractional portion of a vector register relative to the widest supported SEW. In general, implementations must support LMUL >= SEW_MIN/ELEN, where SEW_MIN is the narrowest supported SEW and ELEN is the widest SEW.

STVAL_WIDTH

0 to 64

None

The number of implemented bits in stval.

Must be greater than or equal to max(PHYS_ADDR_WIDTH, VA_SIZE)

STVEC_MODES

1-element to 2-element array of [0, 1]

None

Options:

0: Direct; All traps set pc to stvec.BASE
1: Vectored; Asynchronous interrupts set pc to stvec.BASE + 4 x cause.

If only one mode is given, stvec.MODE is assumed to be read-only with that value. Otherwise, stvec.MODE is read-write.

SUPPORT_FRACTIONAL_LMUL_BEYOND_REQUIRED

[no_unrequired_supported, custom]

Zvl32ba

None

For a given supported fractional LMUL setting, implementations must provide support for SEW settings covering the range from SEW_MIN up to LMUL * ELEN, inclusive. This ensures types narrower than the maximum SEW are supported when fractional LMULs are selected.

SXLEN

1-element to 2-element array of [32, 64]

(MXLEN == 32 → !64 in SXLEN)

Set of XLENs supported in S-mode. Can be one of:

[32]: SXLEN is always 32
[64]: SXLEN is always 64
[32, 64]: SXLEN can be changed (via mstatus.SXL) between 32 and 64

S_MODE_ENDIANNESS

[little, big, dynamic]

None

Endianness of data in S-mode. Can be one of:

little: S-mode data is always little endian
big: S-mode data is always big endian
dynamic: S-mode data can be either little or big endian, depending on the CSR field mstatus.SBE

TIME_CSR_IMPLEMENTED

boolean

Zicntra

None

Whether or not a real hardware time CSR exists. Implementations can either provide a real CSR or emulate access at M-mode.

Possible values:

true: time/timeh exists, and accessing it will not cause an IllegalInstruction trap
false: time/timeh does not exist. Accessing the CSR will cause an IllegalInstruction trap or enter an unpredictable state, depending on TRAP_ON_UNIMPLEMENTED_CSR. Privileged software may emulate the time CSR, or may pass the exception to a lower level.

TINST_VALUE_ON_BREAKPOINT

[always zero, custom]

None

Value written into htinst/mtinst on a Breakpoint exception from VU/VS-mode.

Possible values: * "always zero": Always write the value zero * "custom": Write a custom value, which results in UNPREDICTABLE

TINST_VALUE_ON_FINAL_INSTRUCTION_GUEST_PAGE_FAULT

[always zero, always pseudoinstruction]

None

Value written into htinst/mtinst when there is an instruction guest-page fault on a final translation.

Possible values: * "always zero": Always write the value zero * "always pseudoinstruction": Always write the pseudoinstruction

TINST_VALUE_ON_FINAL_LOAD_GUEST_PAGE_FAULT

[always zero, always pseudoinstruction, always transformed standard instruction, custom]

None

Value written into htinst/mtinst when there is a load guest-page fault on a final translation.

Possible values: * "always zero": Always write the value zero * "always pseudoinstruction": Always write the pseudoinstruction * "always transformed standard instruction": Always write the transformation of the standard instruction encoding * "custom": A custom value, which will cause an UNPREDICTABLE event.

TINST_VALUE_ON_FINAL_STORE_AMO_GUEST_PAGE_FAULT

[always zero, always pseudoinstruction, always transformed standard instruction, custom]

None

Value written into htinst/mtinst when there is a store/AMO guest-page fault on a final translation.

TINST_VALUE_ON_INSTRUCTION_ADDRESS_MISALIGNED

[always zero, custom]

None

Value written into htinst/mtinst when there is an instruction address misaligned exception.

Possible values: * "always zero": Always write the value zero * "custom": Write a custom value, which results in UNPREDICTABLE

TINST_VALUE_ON_LOAD_ACCESS_FAULT

[always zero, always transformed standard instruction, custom]

None

Value written into htinst/mtinst on an AccessFault exception from VU/VS-mode.

Possible values: * "always zero": Always write the value zero * "always transformed standard instruction": Always write a transformed standard instruction as defined by H * "custom": Write a custom value, which results in UNPREDICTABLE

TINST_VALUE_ON_LOAD_ADDRESS_MISALIGNED

[always zero, always transformed standard instruction, custom]

None

Value written into htinst/mtinst on a LoadAddressMisaligned exception from VU/VS-mode.

TINST_VALUE_ON_LOAD_PAGE_FAULT

[always zero, always transformed standard instruction, custom]

None

Value written into htinst/mtinst on a LoadPageFault exception from VU/VS-mode.

TINST_VALUE_ON_MCALL

[always zero, custom]

None

Value written into htinst/mtinst on a MCall exception from VU/VS-mode.

Possible values: * "always zero": Always write the value zero * "custom": Write a custom value, which results in UNPREDICTABLE

TINST_VALUE_ON_SCALL

[always zero, custom]

None

Value written into htinst/mtinst on a SCall exception from VU/VS-mode.

Possible values: * "always zero": Always write the value zero * "custom": Write a custom value, which results in UNPREDICTABLE

TINST_VALUE_ON_STORE_AMO_ACCESS_FAULT

[always zero, always transformed standard instruction, custom]

None

Value written into htinst/mtinst on an AccessFault exception from VU/VS-mode.

TINST_VALUE_ON_STORE_AMO_ADDRESS_MISALIGNED

[always zero, always transformed standard instruction, custom]

None

Value written into htinst/mtinst on a StoreAmoAddressMisaligned exception from VU/VS-mode.

TINST_VALUE_ON_STORE_AMO_PAGE_FAULT

[always zero, always transformed standard instruction, custom]

None

Value written into htinst/mtinst on a StoreAmoPageFault exception from VU/VS-mode.

TINST_VALUE_ON_UCALL

[always zero, custom]

None

Value written into htinst/mtinst on a UCall exception from VU/VS-mode.

Possible values: * "always zero": Always write the value zero * "custom": Write a custom value, which results in UNPREDICTABLE

TINST_VALUE_ON_VIRTUAL_INSTRUCTION

[always zero, custom]

None

Value written into htinst/mtinst on a VirtualInstruction exception from VU/VS-mode.

Possible values: * "always zero": Always write the value zero * "custom": Write a custom value, which results in UNPREDICTABLE

TINST_VALUE_ON_VSCALL

[always zero, custom]

None

Value written into htinst/mtinst on a VSCall exception from VU/VS-mode.

Possible values: * "always zero": Always write the value zero * "custom": Write a custom value, which results in UNPREDICTABLE

TRAP_ON_EBREAK

boolean

Sma

None

The spec states that implementations may handle EBREAKs transparently without raising a trap, in which case the EEI must provide a builtin.

TRAP_ON_ECALL_FROM_M

boolean

Sma

None

The spec states that implementations may handle ECALLs transparently without raising a trap, in which case the EEI must provide a builtin.

TRAP_ON_ECALL_FROM_S

boolean

None

Whether or not an ECALL-from-S-mode causes a synchronous exception.

The spec states that implementations may handle ECALLs transparently without raising a trap, in which case the EEI must provide a builtin.

TRAP_ON_ECALL_FROM_U

boolean

None

Whether or not an ECALL-from-U-mode causes a synchronous exception.

The spec states that implementations may handle ECALLs transparently without raising a trap, in which case the EEI must provide a builtin.

TRAP_ON_ECALL_FROM_VS

boolean

None

Whether or not an ECALL-from-VS-mode causes a synchronous exception.

The spec states that implementations may handle ECALLs transparently without raising a trap, in which case the EEI must provide a builtin.

TRAP_ON_ILLEGAL_WLRL

boolean

Sma

None

Options:

true: Writing an illegal value to a WLRL CSR field will cause an IllegalInstruction exception.
false: Writing an illegal value to a WLRL CSR field causes unpredictable behavior.

TRAP_ON_RESERVED_INSTRUCTION

boolean

Sma

None

Options:

true: Fetching an unimplemented and/or undefined instruction from the standard/reserved opcode space will cause an IllegalInstruction exception.
false: Fetching an unimplemented and/or undefined instruction from the standard/reserved opcose space causes unpredictable behavior.

TRAP_ON_RESERVED_INSTRUCTION may be false while TRAP_ON_UNIMPLEMENTED_INSTRUCTION is true when a custom instruction is implemented in the standard/reserved opcode space.

TRAP_ON_UNIMPLEMENTED_CSR

boolean

Sma

None

Options:

true: Accessing an unimplemented CSR (via a Zicsr instruction) will cause an IllegalInstruction exception.
false: Accessing an unimplemented CSR (via a Zicsr instruction) will cause unpredictable behavior.

TRAP_ON_UNIMPLEMENTED_INSTRUCTION

boolean

Sma

None

Options:

true: Fetching an unimplemented instruction will cause an IllegalInstruction exception.
false: Fetching an unimplemented instruction causes unpredictable behavior.

An unimplemented instruction is any instruction encoding that is not defined by the implementation. Custom instructions are considered implemented.

UXLEN

1-element to 2-element array of [32, 64]

((MXLEN == 32 → !64 in UXLEN) && (32 in SXLEN → 32 in UXLEN))

Set of XLENs supported in U-mode. When both 32 and 64 are supported, UXLEN can be changed, via mstatus.UXL, between 32 and 64.

U_MODE_ENDIANNESS

[little, big, dynamic]

None

Endianness of data in U-mode. Can be one of:

little: U-mode data is always little endian
big: U-mode data is always big endian
dynamic: U-mode data can be either little or big endian, depending on the CSR field mstatus.UBE

VECTOR_FF_NO_EXCEPTION_TRIM

boolean

Zvl32ba

None

Implementations may process fewer than vl elements and reduce vl even when no exception occurs. However, if vstart == 0 and vl > 0, at least one element must be processed.

VECTOR_FF_SEG_EXCEPTION_PARTIAL_LOAD

[no_subsegment_loaded, custom]

Zvl32ba

None

For fault-only-first segment loads, if an exception occurs partway through the zeroth segment, the trap is taken. If it occurs in a subsequent segment, vl may be reduced to the index of that segment. It is implementation-defined whether a partial subset of the segment is loaded before the trap.

VECTOR_FF_UPDATE_PAST_TRIM

[update_none, custom]

Zvl32ba

None

Fault-only-first (FF) load instructions may update active destination elements beyond the index that causes vector-length trimming, but not past the original vl. These spurious updates need not reflect the true memory contents; non-idempotent memory should only be accessed when the load is guaranteed not to be retried.

VECTOR_LOAD_PAST_TRAP

boolean

Zvl32ba

None

Vector load instructions may overwrite active destination vector register group elements past the element index where a trap is reported; the behavior for elements beyond the trap index is implementation-defined.

VECTOR_LOAD_SEG_FF_OVERWRITE_ELEMENTS_AFTER_FAULT

[no_overwrite, custom]

Zvl32ba

None

Fault-only-first segment load instructions may overwrite destination vector register group elements beyond the point where a trap is reported or where vl is trimmed; the exact values written may be implementation-defined.

VECTOR_LS_INDEX_MAX_EEW

[8, 16, 32, 64, XLEN]

Zvl32ba

None

A profile may place an upper limit on the maximum supported index EEW used by vector load/store indexing. For example, some profiles may limit indexing to sizes no larger than XLEN or a fixed EEW value.

VECTOR_LS_MISALIGNED_LEGAL

boolean

Zvl32ba

None

If an element accessed by a vector memory instruction is not naturally aligned to the size of the element, either the element is transferred successfully or an address misaligned exception is raised on that element. Support for misaligned vector memory accesses is independent of an implementation’s support for misaligned scalar memory accesses.

VECTOR_LS_SEG_PARTIAL_ACCESS

boolean

Zvl32ba

None

If a trap occurs during access to a segment, it is implementation-defined whether some, all, or none of that segment’s element accesses are performed before the trap is taken.

VECTOR_LS_WHOLEREG_MISALIGNED_LEGAL

boolean

Zvl32ba

None

Implementations may raise a misaligned address exception for whole-register loads/stores if the base address is not aligned to the maximum of the encoded EEW size (in bytes) or the implementation’s smallest supported SEW (in bytes).

VENDOR_ID_BANK

25-bit integer

Sma

None

Encodes the number of one-byte continuation codes in the Bank field of mvendorid.

iN JEDEC’s parlance, the bank number is one greater than the number of continuation codes; hence, the mvendorid Bank field encodes a value that is one less than the JEDEC bank number.

VENDOR_ID_OFFSET

7-bit integer

Sma

None

Encodes the final byte of a JEDEC manufactor ID, discarding the parity bit.

VFREDUSUM_FINAL_NODE_ELEMENT_BEHAVIOR

[additive_identity, copy]

Zvl32ba

None

Implementations are permitted to insert an additional additive identity into the final reduction result, which may affect the final outcome when no active elements are present.

VFREDUSUM_INACTIVE_NODE_ELEMENT_BEHAVIOR

[additive_identity, copy]

Zvl32ba

None

A reduction node that receives an input derived solely from masked-off elements or elements beyond vl may either treat that input as the additive identity for the appropriate element width or copy the other input through unchanged to the node output.

VFREDUSUM_NAN

[no_change, custom]

Zvl32ba

None

The reduction tree structure must be deterministic for a given vtype and vl; as a consequence, implementations need not preserve NaN payloads when no elements are active. If no elements are active and the scalar input is NaN, implementations may canonicalize it (and raise an exception if it is a signaling NaN) or pass it through unchanged.

VFREDUSUM_NODE_ROUNDING_BEHAVIOR

[SEW_precision, custom]

Zvl32ba

None

Each reduction operator computes an exact sum using an ideal scalar floating-point addition, then converts that result into a floating- point format with range and precision at least as large as the element SEW, rounding with the current dynamic rounding mode and raising exceptions as needed. Implementations may choose the exact range and precision per operator.

VILL_SET_ON_RESERVED_VTYPE

boolean

Zvl32ba

None

Use of vtype encodings with LMUL < SEW_MIN/ELEN is reserved. Implementations may set the vill status bit to indicate such vtype encodings are unsupported, providing a software-visible indication of invalid vtype selections.

VLEN

[32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536]

Zvl32ba

None

The number of bits in a single vector register.

VMID_WIDTH

0 to 14

(MXLEN == 32 → VMID_WIDTH ⇐ 7)

Number of bits supported in hgatp.VMID (i.e., the supported width of a virtual machine ID).

VSSTAGE_MODE_BARE

boolean

(((32 in VSXLEN && SV32_VSMODE_TRANSLATION != true) → VSSTAGE_MODE_BARE == true) && ((((64 in VSXLEN && SV39_VSMODE_TRANSLATION != true) && SV48_VSMODE_TRANSLATION != true) && SV57_VSMODE_TRANSLATION != true) → VSSTAGE_MODE_BARE == true))

Whether or not writing mode=Bare is supported in the vsatp register.

VSSTATUS_VS_EXISTS

boolean

Zvl32ba

None

Some implementations provide a vsstatus.VS field even when the misa.V bit is clear. This parameter indicates whether vsstatus.VS exists independently of the misa.V setting.

VSTVEC_MODES

1-element to 2-element array of [0, 1]

None

Options:

0: Direct; All traps set pc to vstvec.BASE
1: Vectored; Asynchronous interrupts set pc to vstvec.BASE + 4 x cause.

If only one mode is given, vstvec.MODE is assumed to be read-only with that value. Otherwise, vstvec.MODE is read-write.

VSXLEN

1-element to 2-element array of [32, 64]

(!64 in SXLEN → !64 in VSXLEN)

Set of XLENs supported in VS-mode. Can be one of:

[32]: VSXLEN is always 32
[64]: VSXLEN is always 64
[32, 64]: VSXLEN can be changed (via hstatus.VSXL) between 32 and 64

VS_MODE_ENDIANNESS

[little, big, dynamic]

None

Endianness of data in VS-mode. Can be one of:

little: VS-mode data is always little endian
big: VS-mode data is always big endian
dynamic: VS-mode data can be either little or big endian, depending on the CSR field hstatus.VSBE

VUXLEN

1-element to 2-element array of [32, 64]

(!64 in VSXLEN → !64 in VUXLEN)

Set of XLENs supported in VU-mode. When both 32 and 64 are supported, VUXLEN can be changed via vsstatus.UXL.

VU_MODE_ENDIANNESS

[little, big, dynamic]

None

Endianness of data in VU-mode. Can be one of:

little: VU-mode data is always little endian
big: VU-mode data is always big endian
dynamic: VU-mode data can be either little or big endian, depending on the CSR field vsstatus.UBE

ZAWRS_NTO_IS_NOP

boolean

Zawrsa

None