pmpcfg12

PMP Configuration Register 12

PMP entry configuration

Attributes

Requirement

Smpmp

Defining extensions

Smpmp

Physical Memory Protection

CSR Address

0x3ac

Length

* 32 when CSR[misa].MXL == 0 * 64 when CSR[misa].MXL == 1

Privilege Mode

M

Format

This CSR format changes dynamically.

pmpcfg12 Format when CSR[misa].MXL == 0
Figure 1. pmpcfg12 Format when CSR[misa].MXL == 0
pmpcfg12 Format when CSR[misa].MXL == 1
Figure 2. pmpcfg12 Format when CSR[misa].MXL == 1

Field Summary

Name Location Type Reset Value

pmpcfg12.pmp48cfg

7:0

[when,"(NUM_PMP_ENTRIES > 48)"] RW-R [when,"(NUM_PMP_ENTRIES ⇐ 48)"] RO

0

pmpcfg12.pmp49cfg

15:8

[when,"(NUM_PMP_ENTRIES > 49)"] RW-R [when,"(NUM_PMP_ENTRIES ⇐ 49)"] RO

0

pmpcfg12.pmp50cfg

23:16

[when,"(NUM_PMP_ENTRIES > 50)"] RW-R [when,"(NUM_PMP_ENTRIES ⇐ 50)"] RO

0

pmpcfg12.pmp51cfg

31:24

[when,"(NUM_PMP_ENTRIES > 51)"] RW-R [when,"(NUM_PMP_ENTRIES ⇐ 51)"] RO

0

pmpcfg12.pmp52cfg

39:32

[when,"(NUM_PMP_ENTRIES > 52)"] RW-R [when,"(NUM_PMP_ENTRIES ⇐ 52)"] RO

0

pmpcfg12.pmp53cfg

47:40

[when,"(NUM_PMP_ENTRIES > 53)"] RW-R [when,"(NUM_PMP_ENTRIES ⇐ 53)"] RO

0

pmpcfg12.pmp54cfg

55:48

[when,"(NUM_PMP_ENTRIES > 54)"] RW-R [when,"(NUM_PMP_ENTRIES ⇐ 54)"] RO

0

pmpcfg12.pmp55cfg

63:56

[when,"(NUM_PMP_ENTRIES > 55)"] RW-R [when,"(NUM_PMP_ENTRIES ⇐ 55)"] RO

0

Fields

pmp48cfg

Location

7:0

Description

PMP configuration for entry 48

The bits are as follows:

Name Location Description

L

7

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

6:5

Reserved Writes shall be ignored.

A

4:3

Address matching mode. One of:

[when="PMP_GRANULARITY < 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NA4* (2) - Naturally aligned four-byte region
* *NAPOT* (3) - Naturally aligned power of two
[when="PMP_GRANULARITY >= 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NAPOT* (3) - Naturally aligned power of two

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

X

2

When clear, instruction fetches cause an Access Fault for the matching region and privilege mode.

W

1

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

0

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RW-R

RO

Reset value

0

pmp49cfg

Location

15:8

Description

PMP configuration for entry 49

The bits are as follows:

Name Location Description

L

15

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

14:13

Reserved Writes shall be ignored.

A

12:11

Address matching mode. One of:

[when="PMP_GRANULARITY < 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NA4* (2) - Naturally aligned four-byte region
* *NAPOT* (3) - Naturally aligned power of two
[when="PMP_GRANULARITY >= 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NAPOT* (3) - Naturally aligned power of two

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

X

10

When clear, instruction fetches cause an Access Fault for the matching region and privilege mode.

W

9

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

8

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RW-R

RO

Reset value

0

pmp50cfg

Location

23:16

Description

PMP configuration for entry 50

The bits are as follows:

Name Location Description

L

23

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

22:21

Reserved Writes shall be ignored.

A

20:19

Address matching mode. One of:

[when="PMP_GRANULARITY < 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NA4* (2) - Naturally aligned four-byte region
* *NAPOT* (3) - Naturally aligned power of two
[when="PMP_GRANULARITY >= 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NAPOT* (3) - Naturally aligned power of two

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

X

18

When clear, instruction fetches cause an Access Fault for the matching region and privilege mode.

W

17

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

16

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RW-R

RO

Reset value

0

pmp51cfg

Location

31:24

Description

PMP configuration for entry 51

The bits are as follows:

Name Location Description

L

31

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

30:29

Reserved Writes shall be ignored.

A

28:27

Address matching mode. One of:

[when="PMP_GRANULARITY < 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NA4* (2) - Naturally aligned four-byte region
* *NAPOT* (3) - Naturally aligned power of two
[when="PMP_GRANULARITY >= 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NAPOT* (3) - Naturally aligned power of two

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

X

26

When clear, instruction fetches cause an Access Fault for the matching region and privilege mode.

W

25

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

24

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RW-R

RO

Reset value

0

pmp52cfg

Location

39:32

Description

PMP configuration for entry 52

The bits are as follows:

Name Location Description

L

39

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

38:37

Reserved Writes shall be ignored.

A

36:35

Address matching mode. One of:

[when="PMP_GRANULARITY < 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NA4* (2) - Naturally aligned four-byte region
* *NAPOT* (3) - Naturally aligned power of two
[when="PMP_GRANULARITY >= 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NAPOT* (3) - Naturally aligned power of two

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

X

34

When clear, instruction fetches cause an Access Fault for the matching region and privilege mode.

W

33

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

32

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RW-R

RO

Reset value

0

pmp53cfg

Location

47:40

Description

PMP configuration for entry 53

The bits are as follows:

Name Location Description

L

47

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

46:45

Reserved Writes shall be ignored.

A

44:43

Address matching mode. One of:

[when="PMP_GRANULARITY < 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NA4* (2) - Naturally aligned four-byte region
* *NAPOT* (3) - Naturally aligned power of two
[when="PMP_GRANULARITY >= 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NAPOT* (3) - Naturally aligned power of two

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

X

42

When clear, instruction fetches cause an Access Fault for the matching region and privilege mode.

W

41

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

40

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RW-R

RO

Reset value

0

pmp54cfg

Location

55:48

Description

PMP configuration for entry 54

The bits are as follows:

Name Location Description

L

55

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

54:53

Reserved Writes shall be ignored.

A

52:51

Address matching mode. One of:

[when="PMP_GRANULARITY < 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NA4* (2) - Naturally aligned four-byte region
* *NAPOT* (3) - Naturally aligned power of two
[when="PMP_GRANULARITY >= 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NAPOT* (3) - Naturally aligned power of two

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

X

50

When clear, instruction fetches cause an Access Fault for the matching region and privilege mode.

W

49

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

48

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RW-R

RO

Reset value

0

pmp55cfg

Location

63:56

Description

PMP configuration for entry 55

The bits are as follows:

Name Location Description

L

63

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

62:61

Reserved Writes shall be ignored.

A

60:59

Address matching mode. One of:

[when="PMP_GRANULARITY < 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NA4* (2) - Naturally aligned four-byte region
* *NAPOT* (3) - Naturally aligned power of two
[when="PMP_GRANULARITY >= 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NAPOT* (3) - Naturally aligned power of two

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

X

58

When clear, instruction fetches cause an Access Fault for the matching region and privilege mode.

W

57

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

56

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RW-R

RO

Reset value

0

Software write

This CSR may store a value that is different from what software attempts to write.

When a software write occurs (e.g., through csrrw), the following determines the written value:

pmp48cfg = if ((CSR[pmpcfg12].pmp48cfg & 0x80) == 0) {
  # entry is not locked
  if (!(((csr_value.pmp48cfg & 0x1) == 0) && ((csr_value.pmp48cfg & 0x2) == 0x2))) {
    # not R = 0, W =1, which is reserved
    if ((PMP_GRANULARITY < 2) ||
        ((csr_value.pmp48cfg & 0x18) != 0x10)) {
      # NA4 is not allowed when PMP granularity is larger than 4 bytes
      return csr_value.pmp48cfg;
    }
  }
}
# fall through: keep old value
return CSR[pmpcfg12].pmp48cfg;

pmp49cfg = if ((CSR[pmpcfg12].pmp49cfg & 0x80) == 0) {
  # entry is not locked
  if (!(((csr_value.pmp49cfg & 0x1) == 0) && ((csr_value.pmp49cfg & 0x2) == 0x2))) {
    # not R = 0, W =1, which is reserved
    if ((PMP_GRANULARITY < 2) ||
        ((csr_value.pmp49cfg & 0x18) != 0x10)) {
      # NA4 is not allowed when PMP granularity is larger than 4 bytes
      return csr_value.pmp49cfg;
    }
  }
}
# fall through: keep old value
return CSR[pmpcfg12].pmp49cfg;

pmp50cfg = if ((CSR[pmpcfg12].pmp50cfg & 0x80) == 0) {
  # entry is not locked
  if (!(((csr_value.pmp50cfg & 0x1) == 0) && ((csr_value.pmp50cfg & 0x2) == 0x2))) {
    # not R = 0, W =1, which is reserved
    if ((PMP_GRANULARITY < 2) ||
        ((csr_value.pmp50cfg & 0x18) != 0x10)) {
      # NA4 is not allowed when PMP granularity is larger than 4 bytes
      return csr_value.pmp50cfg;
    }
  }
}
# fall through: keep old value
return CSR[pmpcfg12].pmp50cfg;

pmp51cfg = if ((CSR[pmpcfg12].pmp51cfg & 0x80) == 0) {
  # entry is not locked
  if (!(((csr_value.pmp51cfg & 0x1) == 0) && ((csr_value.pmp51cfg & 0x2) == 0x2))) {
    # not R = 0, W =1, which is reserved
    if ((PMP_GRANULARITY < 2) ||
        ((csr_value.pmp51cfg & 0x18) != 0x10)) {
      # NA4 is not allowed when PMP granularity is larger than 4 bytes
      return csr_value.pmp51cfg;
    }
  }
}
# fall through: keep old value
return CSR[pmpcfg12].pmp51cfg;

pmp52cfg = if ((CSR[pmpcfg12].pmp52cfg & 0x80) == 0) {
  # entry is not locked
  if (!(((csr_value.pmp52cfg & 0x1) == 0) && ((csr_value.pmp52cfg & 0x2) == 0x2))) {
    # not R = 0, W =1, which is reserved
    if ((PMP_GRANULARITY < 2) ||
        ((csr_value.pmp52cfg & 0x18) != 0x10)) {
      # NA4 is not allowed when PMP granularity is larger than 4 bytes
      return csr_value.pmp52cfg;
    }
  }
}
# fall through: keep old value
return CSR[pmpcfg12].pmp52cfg;

pmp53cfg = if ((xlen() == 64) && (CSR[pmpcfg12].pmp53cfg & 0x80) == 0) {
  # entry is not locked
  if (!(((csr_value.pmp53cfg & 0x1) == 0) && ((csr_value.pmp53cfg & 0x2) == 0x2))) {
    # not R = 0, W =1, which is reserved
    if ((PMP_GRANULARITY < 2) ||
        ((csr_value.pmp53cfg & 0x18) != 0x10)) {
      # NA4 is not allowed when PMP granularity is larger than 4 bytes
      return csr_value.pmp53cfg;
    }
  }
}
# fall through: keep old value
return CSR[pmpcfg12].pmp53cfg;

pmp54cfg = if ((xlen() == 64) && (CSR[pmpcfg12].pmp54cfg & 0x80) == 0) {
  # entry is not locked
  if (!(((csr_value.pmp54cfg & 0x1) == 0) && ((csr_value.pmp54cfg & 0x2) == 0x2))) {
    # not R = 0, W =1, which is reserved
    if ((PMP_GRANULARITY < 2) ||
        ((csr_value.pmp54cfg & 0x18) != 0x10)) {
      # NA4 is not allowed when PMP granularity is larger than 4 bytes
      return csr_value.pmp54cfg;
    }
  }
}
# fall through: keep old value
return CSR[pmpcfg12].pmp54cfg;

pmp55cfg = if ((xlen() == 64) && (CSR[pmpcfg12].pmp55cfg & 0x80) == 0) {
  # entry is not locked
  if (!(((csr_value.pmp55cfg & 0x1) == 0) && ((csr_value.pmp55cfg & 0x2) == 0x2))) {
    # not R = 0, W =1, which is reserved
    if ((PMP_GRANULARITY < 2) ||
        ((csr_value.pmp55cfg & 0x18) != 0x10)) {
      # NA4 is not allowed when PMP granularity is larger than 4 bytes
      return csr_value.pmp55cfg;
    }
  }
}
# fall through: keep old value
return CSR[pmpcfg12].pmp55cfg;