sip

Supervisor Interrupt Pending

A restricted view of the interrupt pending bits in mip.

Hypervisor-related interrupts (VS-mode interrupts and Supervisor Guest interrupts) are not reflected in sip even though those interrupts can be taken in HS-mode. Instead, they are reported through hip.

Attributes

Requirement

S

Defining extensions

S

Supervisor mode

CSR Address

0x144

Length

* 32 when CSR[mstatus].SXL == 0 * 64 when CSR[mstatus].SXL == 1

Privilege Mode

S

Format

This CSR format changes dynamically.

sip Format when CSR[mstatus].SXL == 0
Figure 1. sip Format when CSR[mstatus].SXL == 0
sip Format when CSR[mstatus].SXL == 1
Figure 2. sip Format when CSR[mstatus].SXL == 1

Field Summary

Name Location Type Reset Value

sip.SSIP

1

RW-R

UNDEFINED_LEGAL

sip.STIP

5

RO-H

UNDEFINED_LEGAL

sip.SEIP

9

RO-H

UNDEFINED_LEGAL

sip.LCOFIP

13

RW-RH

UNDEFINED_LEGAL

Fields

SSIP

Location

1

Description

Supervisor Software Interrupt Pending

Reports the current pending state of an (H)S-mode software interrupt.

When Supervisor Software Interrupts are not delegated to (H)S-mode (mideleg.SSI is clear), sip.SSIP is read-only 0.

Otherwise, sip.SSIP is an alias of mip.SSIP.

<%- if ext?(:Smaia) -%> When using AIA/IMSIC, IPIs are expected to be delivered as external interrupts and SSIP is not backed by any hardware update (aside from any aliasing effects).

However, SSIP is still writable by S-mode software and, when written, can be used to generate an S-mode Software Interrupt. <%- end -%>

Since it is an alias, writes to sip.SSIP are also be reflected in mip.SSIP<% if ext?(:Smaia) %> and mvip.SSIP<% end %>.

<% if ext?(:Smaia) %>_Aliases_<% else %>_Alias_<% end %>:

To summarize:

mideleg.SSI sip.SSIP behavior

0

read-only 0

1

writable alias of mip.SSIP <% if ext?(:Smaia) %>and mvip.SSIP<% end %>
Type

RW-R

Reset value

UNDEFINED_LEGAL

STIP

Location

5

Description

Supervisor Timer Interrupt Pending

Reports the current pending state of an (H)S-mode timer interrupt.

When Supervisor Timer Interrupts are not delegated to (H)S-mode (i.e., mideleg.STI is clear), sip.STIP is read-only 0.

Otherwise, sip.STIP is a read-only view of mip.STIP.

<% if ext?(:Smaia) %>_Aliases_<% else %>_Alias_<% end %>:

To summarize:

mideleg.STI sip.STIP behavior

0

read-only 0

1

read-only alias of mip.STIP <% if ext?(:Smaia) %>(and mvip.STIP when menvcfg.STCE is clear)<% end %>
Type

RO-H

Reset value

UNDEFINED_LEGAL

SEIP

Location

9

Description

Supervisor External Interrupt Pending

Reports the current pending state of an (H)S-mode external interrupt.

When Supervisor External Interrupts are not delegated to (H)S-mode (i.e., mideleg.SEI is clear), sip.SEIP is read-only 0.

Otherwise, sip.SEIP is a read-only view of mip.SEIP.

To summarize:

mideleg.SEI sip.SEIP behavior

0

read-only 0

1

read-only alias of mip.SEIP
Type

RO-H

Reset value

UNDEFINED_LEGAL

LCOFIP

Location

13

Description

Local Counter Overflow Interrupt pending

Reports the current pending state of a Local Counter Overflow interrupt.

When Local Counter Overflow interrupts are not delegated to (H)S-mode (i.e., mideleg.LCOFI is clear), sip.LCOFIP is read-only 0.

Otherwise, sip.LCOFIP is an alias of mip.LCOFIP.

Software writes 0 to sip.LCOFIP to clear the pending interrupt.

To summarize:

mideleg.LCOFI sip.LCOFIP behavior

0

read-only 0

1

writable alias of mip.LCOFIP (and vsip.LCOFIP when hideleg.LCOFI is set)
Type

RW-RH

Reset value

UNDEFINED_LEGAL

Software write

This CSR may store a value that is different from what software attempts to write.

When a software write occurs (e.g., through csrrw), the following determines the written value:

SSIP = if (CSR[mideleg].SSI == 1'b1) {
  CSR[mip].SSIP = csr_value.SSIP;
  return csr_value.SSIP;
}
return 1'b0;

STIP = csr_value.STIP
SEIP = csr_value.SEIP
LCOFIP = if (CSR[mideleg].LCOFI == 1'b1) {
  CSR[mip].LCOFIP = csr_value.LCOFIP;
  return csr_value.LCOFIP;
}
return 1'b0;

Software read

This CSR may return a value that is different from what is stored in hardware.

return $bits(CSR[CSR[mip]]) & $bits(CSR[CSR[mideleg]]);