Implemented Instructions

andn AND with inverted operand

orn OR with inverted operand

rev8 Byte-reverse register (RV64 encoding)

rol Rotate left (Register)

rolw Rotate left word (Register)

ror Rotate right (Register)

rori Rotate right (Immediate)

roriw Rotate right word (Immediate)

rorw Rotate right word (Register)

xnor Exclusive NOR

c.add Add

c.addi Add a sign-extended non-zero immediate

c.addi16sp Add a sign-extended non-zero immediate

c.addi4spn Add a zero-extended non-zero immediate, scaled by 4, to the stack pointer

c.addiw Add a sign-extended non-zero immediate

c.addw Add word

c.and And

c.andi And immediate

c.beqz Branch if Equal Zero

c.bnez Branch if NOT Equal Zero

c.ebreak Breakpoint exception

c.j Jump

c.jalr Jump and Link Register

c.jr Jump Register

c.ld Load double

c.ldsp Load doubleword from stack pointer

c.li Load the sign-extended 6-bit immediate

c.lui Load Upper Immediate

c.lw Load word

c.lwsp Load word from stack pointer

c.mv Move Register

c.nop Non-operation

c.or Or

c.sd Store double

c.sdsp Store doubleword to stack

c.slli Shift left logical immediate

c.srai Shift right arithmetical immediate

c.srli Shift right logical immediate

c.sub Subtract

c.subw Subtract word

c.sw Store word

c.swsp Store word to stack

c.xor Exclusive Or

fadd.d Floating-Point Add Double-Precision

fclass.d Floating-Point Classify Double-Precision

fcvt.d.l Floating-Point Convert Long to Double-Precision

fcvt.d.lu Floating-Point Convert Unsigned Long to Double-Precision

fcvt.d.s Floating-Point Convert Single-Precision to Double-Precision

fcvt.d.w Floating-Point Convert Word to Double-Precision

fcvt.d.wu Floating-Point Convert Unsigned Word to Double-Precision

fcvt.l.d Floating-Point Convert Double-Precision to Long

fcvt.lu.d Floating-Point Convert Double-Precision to Unsigned Long

fcvt.s.d Floating-Point Convert Double-Precision to Single-Precision

fcvt.w.d Floating-Point Convert Double-Precision to Word

fcvt.wu.d Floating-Point Convert Double-Precision to Unsigned Word

fdiv.d Floating-Point Divide Double-Precision

feq.d Floating-Point Equal Double-Precision

fld Floating-Point Load Double-Precision

fle.d Floating-Point Less Than or Equal Double-Precision

flt.d Floating-Point Less Than Double-Precision

fmadd.d Floating-Point Multiply-Add Double-Precision

fmax.d Floating-Point Maximum-Number Double-Precision

fmin.d Floating-Point Minimum-Number Double-Precision

fmsub.d Floating-Point Multiply-Subtract Double-Precision

fmul.d Floating-Point Multiply Double-Precision

fmv.d.x Floating-Point Move Double-Precision from Integer Register

fmv.x.d Floating-Point Move Double-Precision to Integer Register

fnmadd.d Floating-Point Negate-Multiply-Add Double-Precision

fnmsub.d Floating-Point Negate-Multiply-Subtract Double-Precision

fsd Floating-Point Store Double-Precision

fsgnj.d Floating-Point Sign-Inject Double-Precision

fsgnjn.d Floating-Point Sign-Inject Negate Double-Precision

fsgnjx.d Floating-Point Sign-Inject XOR Double-Precision

fsqrt.d Floating-Point Square Root Double-Precision

fsub.d Floating-Point Subtract Double-Precision

fadd.s Floating-Point Add Single-Precision

fclass.s Floating-Point Classify Single-Precision

fcvt.l.s Floating-Point Convert Single-Precision to Long

fcvt.lu.s Floating-Point Convert Single-Precision to Unsigned Long

fcvt.s.l Floating-Point Convert Long to Single-Precision

fcvt.s.lu Floating-Point Convert Unsigned Long to Single-Precision

fcvt.s.w Floating-Point Convert Word to Single-Precision

fcvt.s.wu Floating-Point Convert Unsigned Word to Single-Precision

fcvt.w.s Floating-Point Convert Single-Precision to Word

fcvt.wu.s Floating-Point Convert Single-Precision to Unsigned Word

fdiv.s Floating-Point Divide Single-Precision

feq.s Floating-Point Equal Single-Precision

fle.s Floating-Point Less Than or Equal Single-Precision

flt.s Floating-Point Less Than Single-Precision

flw Floating-Point Load Single-Precision

fmadd.s Floating-Point Multiply-Add Single-Precision

fmax.s Floating-Point Maximum-Number Single-Precision

fmin.s Floating-Point Minimum-Number Single-Precision

fmsub.s Floating-Point Multiply-Subtract Single-Precision

fmul.s Floating-Point Multiply Single-Precision

fmv.w.x Floating-Point Move Single-Precision Word from Integer Register

fmv.x.w Floating-Point Move Single-Precision Word to Integer Register

fnmadd.s Floating-Point Negate-Multiply-Add Single-Precision

fnmsub.s Floating-Point Negate-Multiply-Subtract Single-Precision

fsgnj.s Floating-Point Sign-Inject Single-Precision

fsgnjn.s Floating-Point Sign-Inject Negate Single-Precision

fsgnjx.s Floating-Point Sign-Inject XOR Single-Precision

fsqrt.s Floating-Point Square Root Single-Precision

fsub.s Floating-Point Subtract Single-Precision

fsw Floating-Point Store Single-Precision

hfence.gvma Hypervisor fence guest-physical address

hfence.vvma Hypervisor fence guest virtual address

hlv.b Hypervisor load byte

hlv.bu Hypervisor load byte unsigned

hlv.d Hypervisor load doubleword

hlv.h Hypervisor load halfword

hlv.hu Hypervisor load halfword unsigned

hlv.w Hypervisor load word

hlv.wu Hypervisor load word unsigned

hlvx.hu Hypervisor load halfword unsigned, executable

hlvx.wu Hypervisor load word unsigned, executable

hsv.b Hypervisor store byte

hsv.d Hypervisor store doubleword

hsv.h Hypervisor store halfword

hsv.w Hypervisor store word

add Integer add

addi Add immediate

addiw Add immediate word

addw Add word

and And

andi And immediate

auipc Add upper immediate to pc

beq Branch if equal

bge Branch if greater than or equal

bgeu Branch if greater than or equal unsigned

blt Branch if less than

bltu Branch if less than unsigned

bne Branch if not equal

ebreak Breakpoint exception

ecall Environment call

fence.tso Memory ordering fence, total store ordering

fence Memory ordering fence

jal Jump and link

jalr Jump and link register

lb Load byte

lbu Load byte unsigned

ld Load doubleword

lh Load halfword

lhu Load halfword unsigned

lui Load upper immediate

lw Load word

lwu Load word unsigned

mret Machine-mode Return from Trap

or Or

ori Or immediate

sb Store byte

sd Store doubleword

sh Store halfword

sll Shift left logical

slli Shift left logical immediate

slliw Shift left logical immediate word

sllw Shift left logical word

slt Set on less than

slti Set on less than immediate

sltiu Set on less than immediate unsigned

sltu Set on less than unsigned

sra Shift right arithmetic

srai Shift right arithmetic immediate

sraiw Shift right arithmetic immediate word

sraw Shift right arithmetic word

srl Shift right logical

srli Shift right logical immediate

srliw Shift right logical immediate word

srlw Shift right logical word

sub Subtract

subw Subtract word

sw Store word

wfi Wait for interrupt

xor Exclusive Or

xori Exclusive Or immediate

div Signed division

divu Unsigned division

divuw Unsigned 32-bit division

divw Signed 32-bit division

mul Signed multiply

mulh Signed multiply high

mulhsu Signed/unsigned multiply high

mulhu Unsigned multiply high

mulw Signed 32-bit multiply

rem Signed remainder

remu Unsigned remainder

remuw Unsigned 32-bit remainder

remw Signed 32-bit remainder

sfence.vma Supervisor memory-management fence

sret Supervisor Mode Return from Trap

vaadd.vv No synopsis available

vaadd.vx No synopsis available

vaaddu.vv No synopsis available

vaaddu.vx No synopsis available

vadc.vim Vector add with carry and masked

vadc.vvm Vector add with carry and masked

vadc.vxm Vector add with carry and scalar, masked

vadd.vi Vector-immediate integer addition

vadd.vv Vector-vector integer addition

vadd.vx Vector-scalar integer addition

vand.vi No synopsis available

vand.vv Vector-vector bitwise AND

vand.vx No synopsis available

vasub.vv No synopsis available

vasub.vx No synopsis available

vasubu.vv No synopsis available

vasubu.vx No synopsis available

vcompress.vm No synopsis available

vcpop.m No synopsis available

vdiv.vv No synopsis available

vdiv.vx No synopsis available

vdivu.vv No synopsis available

vdivu.vx No synopsis available

vfadd.vf Vector floating-point add scalar

vfadd.vv Vector floating-point add

vfclass.v No synopsis available

vfcvt.f.x.v Vector integer to floating-point conversion

vfcvt.f.xu.v Vector unsigned integer to floating-point conversion

vfcvt.rtz.x.f.v Vector floating-point to integer conversion with truncation

vfcvt.rtz.xu.f.v Vector floating-point to unsigned integer conversion with truncation

vfcvt.x.f.v Vector floating-point to integer conversion

vfcvt.xu.f.v Vector floating-point to unsigned integer conversion

vfdiv.vf Vector floating-point divide scalar

vfdiv.vv Vector floating-point divide

vfirst.m No synopsis available

vfmacc.vf No synopsis available

vfmacc.vv No synopsis available

vfmadd.vf No synopsis available

vfmadd.vv No synopsis available

vfmax.vf No synopsis available

vfmax.vv No synopsis available

vfmerge.vfm No synopsis available

vfmin.vf No synopsis available

vfmin.vv No synopsis available

vfmsac.vf No synopsis available

vfmsac.vv No synopsis available

vfmsub.vf No synopsis available

vfmsub.vv No synopsis available

vfmul.vf Vector floating-point multiply scalar

vfmul.vv Vector floating-point multiply

vfmv.f.s Vector floating-point to scalar move

vfmv.s.f Vector scalar to floating-point move

vfmv.v.f Vector floating-point to vector move

vfncvt.f.f.w Vector floating-point widening conversion

vfncvt.f.x.w Vector integer to floating-point widening conversion

vfncvt.f.xu.w Vector unsigned integer to floating-point widening conversion

vfncvt.rod.f.f.w Vector floating-point format conversion with round-to-odd (widening)

vfncvt.rtz.x.f.w Vector floating-point to integer widening conversion with truncation

vfncvt.rtz.xu.f.w Vector floating-point to unsigned integer widening conversion with truncation

vfncvt.x.f.w Vector floating-point to integer widening conversion

vfncvt.xu.f.w Vector floating-point to unsigned integer widening conversion

vfnmacc.vf No synopsis available

vfnmacc.vv No synopsis available

vfnmadd.vf No synopsis available

vfnmadd.vv No synopsis available

vfnmsac.vf No synopsis available

vfnmsac.vv No synopsis available

vfnmsub.vf No synopsis available

vfnmsub.vv No synopsis available

vfrdiv.vf No synopsis available

vfrec7.v No synopsis available

vfredmax.vs No synopsis available

vfredmin.vs No synopsis available

vfredosum.vs No synopsis available

vfredusum.vs No synopsis available

vfrsqrt7.v No synopsis available

vfrsub.vf No synopsis available

vfsgnj.vf No synopsis available

vfsgnj.vv No synopsis available

vfsgnjn.vf No synopsis available

vfsgnjn.vv No synopsis available

vfsgnjx.vf No synopsis available

vfsgnjx.vv No synopsis available

vfslide1down.vf No synopsis available

vfslide1up.vf No synopsis available

vfsqrt.v No synopsis available

vfsub.vf Vector floating-point subtract scalar

vfsub.vv Vector floating-point subtract

vfwadd.vf Vector floating-point widening addition with scalar

vfwadd.vv Vector floating-point widening addition

vfwadd.wf No synopsis available

vfwadd.wv No synopsis available

vfwcvt.f.f.v Vector floating-point widening conversion

vfwcvt.f.x.v Vector integer to floating-point widening conversion

vfwcvt.f.xu.v Vector unsigned integer to floating-point widening conversion

vfwcvt.rtz.x.f.v Vector floating-point to integer widening conversion with truncation

vfwcvt.rtz.xu.f.v Vector floating-point to unsigned integer widening conversion with truncation

vfwcvt.x.f.v Vector floating-point to integer widening conversion

vfwcvt.xu.f.v Vector floating-point to unsigned integer widening conversion

vfwmacc.vf No synopsis available

vfwmacc.vv No synopsis available

vfwmsac.vf No synopsis available

vfwmsac.vv No synopsis available

vfwmul.vf No synopsis available

vfwmul.vv No synopsis available

vfwnmacc.vf No synopsis available

vfwnmacc.vv No synopsis available

vfwnmsac.vf No synopsis available

vfwnmsac.vv No synopsis available

vfwredosum.vs No synopsis available

vfwredusum.vs No synopsis available

vfwsub.vf Vector floating-point widening subtraction with scalar

vfwsub.vv Vector floating-point widening subtraction

vfwsub.wf No synopsis available

vfwsub.wv No synopsis available

vid.v No synopsis available

viota.m No synopsis available

vl1re16.v Vector load 1 element of 16 bits with register stride

vl1re32.v Vector load 1 element of 32 bits with register stride

vl1re64.v Vector load 1 element of 64 bits with register stride

vl1re8.v Vector load 1 element of 8 bits with register stride

vl2re16.v Vector load 2 elements of 16 bits with register stride

vl2re32.v Vector load 2 elements of 32 bits with register stride

vl2re64.v Vector load 2 elements of 64 bits with register stride

vl2re8.v Vector load 2 elements of 8 bits with register stride

vl4re16.v Vector load 4 elements of 16 bits with register stride

vl4re32.v Vector load 4 elements of 32 bits with register stride

vl4re64.v Vector load 4 elements of 64 bits with register stride

vl4re8.v Vector load 4 elements of 8 bits with register stride

vl8re16.v Vector load 8 elements of 16 bits with register stride

vl8re32.v Vector load 8 elements of 32 bits with register stride

vl8re64.v Vector load 8 elements of 64 bits with register stride

vl8re8.v Vector load 8 elements of 8 bits with register stride

vle16.v Vector load 16-bit elements

vle16ff.v Vector load 16-bit elements, fault-first

vle32.v Vector load 32-bit elements

vle32ff.v Vector load 32-bit elements, fault-first

vle64.v Vector load 64-bit elements

vle64ff.v Vector load 64-bit elements, fault-first

vle8.v Vector 8-bit unit-stride load

vle8ff.v Vector load 8-bit elements, fault-first

vlm.v Vector load mask

vloxei16.v Vector ordered load 1 element of 16 bits with index

vloxei32.v Vector ordered load 1 element of 32 bits with index

vloxei64.v Vector ordered load 1 element of 64 bits with index

vloxei8.v Vector ordered load 1 element of 8 bits with index

vloxseg2ei16.v Vector ordered load 2 elements of 16 bits with index

vloxseg2ei32.v Vector ordered load 2 elements of 32 bits with index

vloxseg2ei64.v Vector ordered load 2 elements of 64 bits with index

vloxseg2ei8.v Vector ordered load 2 elements of 8 bits with index

vloxseg3ei16.v Vector ordered load 3 elements of 16 bits with index

vloxseg3ei32.v Vector ordered load 3 elements of 32 bits with index

vloxseg3ei64.v Vector ordered load 3 elements of 64 bits with index

vloxseg3ei8.v Vector ordered load 3 elements of 8 bits with index

vloxseg4ei16.v Vector ordered load 4 elements of 16 bits with index

vloxseg4ei32.v Vector ordered load 4 elements of 32 bits with index

vloxseg4ei64.v Vector ordered load 4 elements of 64 bits with index

vloxseg4ei8.v Vector ordered load 4 elements of 8 bits with index

vloxseg5ei16.v Vector ordered load 5 elements of 16 bits with index

vloxseg5ei32.v Vector ordered load 5 elements of 32 bits with index

vloxseg5ei64.v Vector ordered load 5 elements of 64 bits with index

vloxseg5ei8.v Vector ordered load 5 elements of 8 bits with index

vloxseg6ei16.v Vector ordered load 6 elements of 16 bits with index

vloxseg6ei32.v Vector ordered load 6 elements of 32 bits with index

vloxseg6ei64.v Vector ordered load 6 elements of 64 bits with index

vloxseg6ei8.v Vector ordered load 6 elements of 8 bits with index

vloxseg7ei16.v Vector ordered load 7 elements of 16 bits with index

vloxseg7ei32.v Vector ordered load 7 elements of 32 bits with index

vloxseg7ei64.v Vector ordered load 7 elements of 64 bits with index

vloxseg7ei8.v Vector ordered load 7 elements of 8 bits with index

vloxseg8ei16.v Vector ordered load 8 elements of 16 bits with index

vloxseg8ei32.v Vector ordered load 8 elements of 32 bits with index

vloxseg8ei64.v Vector ordered load 8 elements of 64 bits with index

vloxseg8ei8.v Vector ordered load 8 elements of 8 bits with index

vlse16.v Vector load 16-bit elements with stride

vlse32.v Vector load 32-bit elements with stride

vlse64.v Vector strided load 64-bit elements

vlse8.v Vector load 8-bit elements with stride

vlseg2e16.v Vector segmented load 2 elements of 16 bits

vlseg2e16ff.v Vector segmented load 2 elements of 16 bits, fault-first

vlseg2e32.v Vector segmented load 2 elements of 32 bits

vlseg2e32ff.v Vector segmented load 2 elements of 32 bits, fault-first

vlseg2e64.v Vector segmented load 2 elements of 64 bits

vlseg2e64ff.v Vector segmented load 2 elements of 64 bits, fault-first

vlseg2e8.v Vector segmented load 2 elements of 8 bits

vlseg2e8ff.v Vector segmented load 2 elements of 8 bits, fault-first

vlseg3e16.v Vector segmented load 3 elements of 16 bits

vlseg3e16ff.v Vector segmented load 3 elements of 16 bits, fault-first

vlseg3e32.v Vector segmented load 3 elements of 32 bits

vlseg3e32ff.v Vector segmented load 3 elements of 32 bits, fault-first

vlseg3e64.v Vector segmented load 3 elements of 64 bits

vlseg3e64ff.v Vector segmented load 3 elements of 64 bits, fault-first

vlseg3e8.v Vector segmented load 3 elements of 8 bits

vlseg3e8ff.v Vector segmented load 3 elements of 8 bits, fault-first

vlseg4e16.v Vector segmented load 4 elements of 16 bits

vlseg4e16ff.v Vector segmented load 4 elements of 16 bits, fault-first

vlseg4e32.v Vector segmented load 4 elements of 32 bits

vlseg4e32ff.v Vector segmented load 4 elements of 32 bits, fault-first

vlseg4e64.v Vector segmented load 4 elements of 64 bits

vlseg4e64ff.v Vector segmented load 4 elements of 64 bits, fault-first

vlseg4e8.v Vector segmented load 4 elements of 8 bits

vlseg4e8ff.v Vector segmented load 4 elements of 8 bits, fault-first

vlseg5e16.v Vector segmented load 5 elements of 16 bits

vlseg5e16ff.v Vector segmented load 5 elements of 16 bits, fault-first

vlseg5e32.v Vector segmented load 5 elements of 32 bits

vlseg5e32ff.v Vector segmented load 5 elements of 32 bits, fault-first

vlseg5e64.v Vector segmented load 5 elements of 64 bits

vlseg5e64ff.v Vector segmented load 5 elements of 64 bits, fault-first

vlseg5e8.v Vector segmented load 5 elements of 8 bits

vlseg5e8ff.v Vector segmented load 5 elements of 8 bits, fault-first

vlseg6e16.v Vector segmented load 6 elements of 16 bits

vlseg6e16ff.v Vector segmented load 6 elements of 16 bits, fault-first

vlseg6e32.v Vector segmented load 6 elements of 32 bits

vlseg6e32ff.v Vector segmented load 6 elements of 32 bits, fault-first

vlseg6e64.v Vector segmented load 6 elements of 64 bits

vlseg6e64ff.v Vector segmented load 6 elements of 64 bits, fault-first

vlseg6e8.v Vector segmented load 6 elements of 8 bits

vlseg6e8ff.v Vector segmented load 6 elements of 8 bits, fault-first

vlseg7e16.v Vector segmented load 7 elements of 16 bits

vlseg7e16ff.v Vector segmented load 7 elements of 16 bits, fault-first

vlseg7e32.v Vector segmented load 7 elements of 32 bits

vlseg7e32ff.v Vector segmented load 7 elements of 32 bits, fault-first

vlseg7e64.v Vector segmented load 7 elements of 64 bits

vlseg7e64ff.v Vector segmented load 7 elements of 64 bits, fault-first

vlseg7e8.v Vector segmented load 7 elements of 8 bits

vlseg7e8ff.v Vector segmented load 7 elements of 8 bits, fault-first

vlseg8e16.v Vector segmented load 8 elements of 16 bits

vlseg8e16ff.v Vector segmented load 8 elements of 16 bits, fault-first

vlseg8e32.v Vector segmented load 8 elements of 32 bits

vlseg8e32ff.v Vector segmented load 8 elements of 32 bits, fault-first

vlseg8e64.v Vector segmented load 8 elements of 64 bits

vlseg8e64ff.v Vector segmented load 8 elements of 64 bits, fault-first

vlseg8e8.v Vector segmented load 8 elements of 8 bits

vlseg8e8ff.v Vector segmented load 8 elements of 8 bits, fault-first

vlsseg2e16.v Vector segmented load 2 elements of 16 bits with stride

vlsseg2e32.v Vector segmented load 2 elements of 32 bits with stride

vlsseg2e64.v Vector strided load 2 elements of 64 bits

vlsseg2e8.v Vector segmented load 2 elements of 8 bits with stride

vlsseg3e16.v Vector segmented load 3 elements of 16 bits with stride

vlsseg3e32.v Vector segmented load 3 elements of 32 bits with stride

vlsseg3e64.v Vector segmented load 3 elements of 64 bits with stride

vlsseg3e8.v Vector segmented load 3 elements of 8 bits with stride

vlsseg4e16.v Vector segmented load 4 elements of 16 bits with stride

vlsseg4e32.v Vector segmented load 4 elements of 32 bits with stride

vlsseg4e64.v Vector strided load 4 elements of 64 bits

vlsseg4e8.v Vector strided load 4 elements of 8 bits

vlsseg5e16.v Vector segmented load 5 elements of 16 bits with stride

vlsseg5e32.v Vector segmented load 5 elements of 32 bits with stride

vlsseg5e64.v Vector segmented load 5 elements of 64 bits with stride

vlsseg5e8.v Vector strided load 5 elements of 8 bits

vlsseg6e16.v Vector strided load 6 elements of 16 bits

vlsseg6e32.v Vector strided load 6 elements of 32 bits

vlsseg6e64.v Vector segmented load 6 elements of 64 bits with stride

vlsseg6e8.v Vector segmented load 6 elements of 8 bits with stride

vlsseg7e16.v Vector strided load 7 elements of 16 bits

vlsseg7e32.v Vector segmented load 7 elements of 32 bits with stride

vlsseg7e64.v Vector segmented load 7 elements of 64 bits with stride

vlsseg7e8.v Vector segmented load 7 elements of 8 bits with stride

vlsseg8e16.v Vector segmented load 8 elements of 16 bits with stride

vlsseg8e32.v Vector segmented load 8 elements of 32 bits with stride

vlsseg8e64.v Vector segmented load 8 elements of 64 bits with stride

vlsseg8e8.v Vector segmented load 8 elements of 8 bits with stride

vluxei16.v Vector unordered load 1 element of 16 bits with index

vluxei32.v Vector unordered load 1 element of 32 bits with index

vluxei64.v Vector unordered load 1 element of 64 bits with index

vluxei8.v Vector unordered load 1 element of 8 bits with index

vluxseg2ei16.v No synopsis available

vluxseg2ei32.v No synopsis available

vluxseg2ei64.v Vector unordered load 2 elements of 64 bits with index

vluxseg2ei8.v Vector unordered load 2 elements of 8 bits with index

vluxseg3ei16.v Vector unordered load 3 elements of 16 bits with index

vluxseg3ei32.v Vector unordered load 3 elements of 32 bits with index

vluxseg3ei64.v Vector unordered load 3 elements of 64 bits with index

vluxseg3ei8.v Vector unordered load 3 elements of 8 bits with index

vluxseg4ei16.v Vector unordered load 4 elements of 16 bits with index

vluxseg4ei32.v Vector unordered load 4 elements of 32 bits with index

vluxseg4ei64.v Vector unordered load 4 elements of 64 bits with index

vluxseg4ei8.v Vector unordered load 4 elements of 8 bits with index

vluxseg5ei16.v Vector unordered load 5 elements of 16 bits with index

vluxseg5ei32.v Vector unordered load 5 elements of 32 bits with index

vluxseg5ei64.v Vector unordered load 5 elements of 64 bits with index

vluxseg5ei8.v Vector unordered load 5 elements of 8 bits with index

vluxseg6ei16.v Vector unordered load 6 elements of 16 bits with index

vluxseg6ei32.v Vector unordered load 6 elements of 32 bits with index

vluxseg6ei64.v Vector unordered load 6 elements of 64 bits with index

vluxseg6ei8.v Vector unordered load 6 elements of 8 bits with index

vluxseg7ei16.v Vector unordered load 7 elements of 16 bits with index

vluxseg7ei32.v Vector unordered load 7 elements of 32 bits with index

vluxseg7ei64.v Vector unordered load 7 elements of 64 bits with index

vluxseg7ei8.v Vector unordered load 7 elements of 8 bits with index

vluxseg8ei16.v Vector unordered load 8 elements of 16 bits with index

vluxseg8ei32.v Vector unordered load 8 elements of 32 bits with index

vluxseg8ei64.v Vector unordered load 8 elements of 64 bits with index

vluxseg8ei8.v Vector unordered load 8 elements of 8 bits with index

vmacc.vv No synopsis available

vmacc.vx No synopsis available

vmadc.vi Vector multiply-add with carry and immediate

vmadc.vim Vector multiply-add with carry and masked

vmadc.vv Vector multiply-add with carry

vmadc.vvm Vector multiply-add with carry and masked

vmadc.vx Vector multiply-add with carry and scalar

vmadc.vxm Vector multiply-add with carry and scalar, masked

vmadd.vv No synopsis available

vmadd.vx No synopsis available

vmand.mm No synopsis available

vmandn.mm No synopsis available

vmax.vv No synopsis available

vmax.vx No synopsis available

vmaxu.vv No synopsis available

vmaxu.vx No synopsis available

vmerge.vim No synopsis available

vmerge.vvm Vector merge with mask

vmerge.vxm No synopsis available

vmfeq.vf No synopsis available

vmfeq.vv No synopsis available

vmfge.vf No synopsis available

vmfgt.vf No synopsis available

vmfle.vf No synopsis available

vmfle.vv No synopsis available

vmflt.vf No synopsis available

vmflt.vv No synopsis available

vmfne.vf No synopsis available

vmfne.vv No synopsis available

vmin.vv No synopsis available

vmin.vx No synopsis available

vminu.vv No synopsis available

vminu.vx No synopsis available

vmnand.mm No synopsis available

vmnor.mm No synopsis available

vmor.mm No synopsis available

vmorn.mm No synopsis available

vmsbc.vv Vector multiply-subtract with carry

vmsbc.vvm No synopsis available

vmsbc.vx Vector multiply-subtract with carry and scalar

vmsbc.vxm No synopsis available

vmsbf.m No synopsis available

vmseq.vi Vector mask equal immediate

vmseq.vv Vector mask equal

vmseq.vx Vector mask equal scalar

vmsgt.vi Vector mask greater than signed immediate

vmsgt.vx Vector mask greater than signed scalar

vmsgtu.vi Vector mask greater than unsigned immediate

vmsgtu.vx Vector mask greater than unsigned scalar

vmsif.m No synopsis available

vmsle.vi Vector mask less than or equal signed immediate

vmsle.vv Vector mask less than or equal signed

vmsle.vx Vector mask less than or equal signed scalar

vmsleu.vi Vector mask less than or equal unsigned immediate

vmsleu.vv Vector mask less than or equal unsigned

vmsleu.vx Vector mask less than or equal unsigned scalar

vmslt.vv Vector mask less than signed

vmslt.vx Vector mask less than signed scalar

vmsltu.vv Vector mask less than unsigned

vmsltu.vx Vector mask less than unsigned scalar

vmsne.vi Vector mask not equal immediate

vmsne.vv Vector mask not equal

vmsne.vx Vector mask not equal scalar

vmsof.m No synopsis available

vmul.vv No synopsis available

vmul.vx No synopsis available

vmulh.vv No synopsis available

vmulh.vx No synopsis available

vmulhsu.vv No synopsis available

vmulhsu.vx No synopsis available

vmulhu.vv No synopsis available

vmulhu.vx No synopsis available

vmv.s.x No synopsis available

vmv.v.i Vector move immediate to vector register

vmv.v.v Vector register move

vmv.v.x Vector scalar to vector move

vmv.x.s No synopsis available

vmv1r.v No synopsis available

vmv2r.v No synopsis available

vmv4r.v No synopsis available

vmv8r.v No synopsis available

vmxnor.mm No synopsis available

vmxor.mm No synopsis available

vnclip.wi Vector widening signed clip with immediate

vnclip.wv Vector widening signed clip

vnclip.wx Vector widening signed clip with scalar

vnclipu.wi Vector widening unsigned clip with immediate

vnclipu.wv Vector widening unsigned clip

vnclipu.wx Vector widening unsigned clip with scalar

vnmsac.vv No synopsis available

vnmsac.vx No synopsis available

vnmsub.vv No synopsis available

vnmsub.vx No synopsis available

vnsra.wi Vector widening signed shift right arithmetic with immediate

vnsra.wv Vector widening signed shift right arithmetic

vnsra.wx Vector widening signed shift right arithmetic with scalar

vnsrl.wi Vector widening logical shift right with immediate

vnsrl.wv Vector widening logical shift right

vnsrl.wx Vector widening logical shift right with scalar

vor.vi Vector bitwise OR with immediate

vor.vv Vector-vector bitwise OR

vor.vx Vector bitwise OR with scalar

vredand.vs No synopsis available

vredmax.vs No synopsis available

vredmaxu.vs No synopsis available

vredmin.vs No synopsis available

vredminu.vs No synopsis available

vredor.vs No synopsis available

vredsum.vs No synopsis available

vredxor.vs No synopsis available

vrem.vv Vector remainder

vrem.vx Vector remainder with scalar

vremu.vv Vector unsigned remainder

vremu.vx Vector unsigned remainder with scalar

vrgather.vi Vector register gather with immediate index

vrgather.vv Vector register gather

vrgather.vx Vector register gather with scalar index

vrgatherei16.vv No synopsis available

vrsub.vi Vector reverse subtract with immediate

vrsub.vx Vector reverse subtract with scalar

vs1r.v Vector store 1 element with register stride

vs2r.v Vector store 2 elements

vs4r.v Vector store 4 elements

vs8r.v Vector store 8 elements with register stride

vsadd.vi Vector unsigned addition with immediate

vsadd.vv Vector unsigned addition

vsadd.vx Vector unsigned addition with scalar

vsaddu.vi Vector signed addition with immediate

vsaddu.vv Vector signed addition

vsaddu.vx Vector signed addition with scalar

vsbc.vvm Vector subtract with borrow and masked

vsbc.vxm Vector subtract with borrow and scalar, masked

vse16.v Vector store 16-bit elements

vse32.v Vector store 32-bit elements

vse64.v Vector store 64-bit elements

vse8.v Vector 8-bit unit-stride store

vsetivli Vector Set Vector Type Immediate and Vector Length Immediate

vsetvl Vector Set Vector Type and Vector Length

vsetvli Set vector length immediate

vsext.vf2 Vector sign-extend by factor of 2

vsext.vf4 Vector sign-extend by factor of 4

vsext.vf8 Vector sign-extend by factor of 8

vslide1down.vx Vector slide down by 1 element with scalar

vslide1up.vx Vector slide up by 1 element with scalar

vslidedown.vi Vector slide down with immediate

vslidedown.vx Vector slide down with scalar

vslideup.vi Vector slide up with immediate

vslideup.vx Vector slide up with scalar

vsll.vi Vector shift left logical immediate

vsll.vv Vector shift left logical

vsll.vx Vector shift left logical scalar

vsm.v Vector store mask

vsmul.vv Vector signed multiplication

vsmul.vx Vector signed multiplication with scalar

vsoxei16.v Vector ordered store 1 element of 16 bits with index

vsoxei32.v Vector ordered store 1 element of 32 bits with index

vsoxei64.v Vector ordered store 1 element of 64 bits with index

vsoxei8.v Vector ordered store 1 element of 8 bits with index

vsoxseg2ei16.v Vector ordered store 2 elements of 16 bits with index

vsoxseg2ei32.v Vector ordered store 2 elements of 32 bits with index

vsoxseg2ei64.v Vector ordered store 2 elements of 64 bits with index

vsoxseg2ei8.v Vector ordered store 2 elements of 8 bits with index

vsoxseg3ei16.v Vector ordered store 3 elements of 16 bits with index

vsoxseg3ei32.v Vector ordered store 3 elements of 32 bits with index

vsoxseg3ei64.v Vector ordered store 3 elements of 64 bits with index

vsoxseg3ei8.v Vector ordered store 3 elements of 8 bits with index

vsoxseg4ei16.v Vector ordered store 4 elements of 16 bits with index

vsoxseg4ei32.v Vector ordered store 4 elements of 32 bits with index

vsoxseg4ei64.v Vector ordered store 4 elements of 64 bits with index

vsoxseg4ei8.v Vector ordered store 4 elements of 8 bits with index

vsoxseg5ei16.v Vector ordered store 5 elements of 16 bits with index

vsoxseg5ei32.v Vector ordered store 5 elements of 32 bits with index

vsoxseg5ei64.v Vector ordered store 5 elements of 64 bits with index

vsoxseg5ei8.v Vector ordered store 5 elements of 8 bits with index

vsoxseg6ei16.v Vector ordered store 6 elements of 16 bits with index

vsoxseg6ei32.v Vector ordered store 6 elements of 32 bits with index

vsoxseg6ei64.v Vector ordered store 6 elements of 64 bits with index

vsoxseg6ei8.v Vector ordered store 6 elements of 8 bits with index

vsoxseg7ei16.v Vector ordered store 7 elements of 16 bits with index

vsoxseg7ei32.v Vector ordered store 7 elements of 32 bits with index

vsoxseg7ei64.v Vector ordered store 7 elements of 64 bits with index

vsoxseg7ei8.v Vector ordered store 7 elements of 8 bits with index

vsoxseg8ei16.v Vector ordered store 8 elements of 16 bits with index

vsoxseg8ei32.v Vector ordered store 8 elements of 32 bits with index

vsoxseg8ei64.v Vector ordered store 8 elements of 64 bits with index

vsoxseg8ei8.v Vector ordered store 8 elements of 8 bits with index

vsra.vi Vector shift right arithmetic immediate

vsra.vv Vector shift right arithmetic

vsra.vx Vector shift right arithmetic scalar

vsrl.vi Vector shift right logical immediate

vsrl.vv Vector shift right logical

vsrl.vx Vector shift right logical scalar

vsse16.v Vector strided store 16-bit elements

vsse32.v Vector strided store 32-bit elements

vsse64.v Vector store 64-bit elements with stride

vsse8.v Vector store 8-bit elements with stride

vsseg2e16.v Vector segmented store 2 elements of 16 bits

vsseg2e32.v Vector segmented store 2 elements of 32 bits

vsseg2e64.v Vector segmented store 2 elements of 64 bits

vsseg2e8.v Vector segmented store 2 elements of 8 bits

vsseg3e16.v Vector segmented store 3 elements of 16 bits

vsseg3e32.v Vector segmented store 3 elements of 32 bits

vsseg3e64.v Vector segmented store 3 elements of 64 bits

vsseg3e8.v Vector segmented store 3 elements of 8 bits

vsseg4e16.v Vector segmented store 4 elements of 16 bits

vsseg4e32.v Vector segmented store 4 elements of 32 bits

vsseg4e64.v Vector segmented store 4 elements of 64 bits

vsseg4e8.v Vector segmented store 4 elements of 8 bits

vsseg5e16.v Vector segmented store 5 elements of 16 bits

vsseg5e32.v Vector segmented store 5 elements of 32 bits

vsseg5e64.v Vector segmented store 5 elements of 64 bits

vsseg5e8.v Vector segmented store 5 elements of 8 bits

vsseg6e16.v Vector segmented store 6 elements of 16 bits

vsseg6e32.v Vector segmented store 6 elements of 32 bits

vsseg6e64.v Vector segmented store 6 elements of 64 bits

vsseg6e8.v Vector segmented store 6 elements of 8 bits

vsseg7e16.v Vector segmented store 7 elements of 16 bits

vsseg7e32.v Vector segmented store 7 elements of 32 bits

vsseg7e64.v Vector segmented store 7 elements of 64 bits

vsseg7e8.v Vector segmented store 7 elements of 8 bits

vsseg8e16.v Vector segmented store 8 elements of 16 bits

vsseg8e32.v Vector segmented store 8 elements of 32 bits

vsseg8e64.v Vector segmented store 8 elements of 64 bits

vsseg8e8.v Vector segmented store 8 elements of 8 bits

vssra.vi Vector signed shift right arithmetic with immediate

vssra.vv Vector signed shift right arithmetic

vssra.vx Vector signed shift right arithmetic with scalar

vssrl.vi Vector shift right logical by immediate

vssrl.vv No synopsis available

vssrl.vx Vector shift right logical by vector

vssseg2e16.v Vector strided store 2 elements of 16 bits

vssseg2e32.v Vector strided store 2 elements of 32 bits

vssseg2e64.v Vector segmented store 2 elements of 64 bits with stride

vssseg2e8.v Vector strided store 2 elements of 8 bits

vssseg3e16.v Vector strided store 3 elements of 16 bits

vssseg3e32.v Vector strided store 3 elements of 32 bits

vssseg3e64.v Vector segmented store 3 elements of 64 bits with stride

vssseg3e8.v Vector strided store 3 elements of 8 bits

vssseg4e16.v Vector strided store 4 elements of 16 bits

vssseg4e32.v Vector strided store 4 elements of 32 bits

vssseg4e64.v Vector segmented store 4 elements of 64 bits with stride

vssseg4e8.v Vector segmented store 4 elements of 8 bits with stride

vssseg5e16.v Vector segmented store 5 elements of 16 bits with stride

vssseg5e32.v Vector segmented store 5 elements of 32 bits with stride

vssseg5e64.v Vector segmented store 5 elements of 64 bits with stride

vssseg5e8.v Vector segmented store 5 elements of 8 bits with stride

vssseg6e16.v Vector segmented store 6 elements of 16 bits with stride

vssseg6e32.v Vector segmented store 6 elements of 32 bits with stride

vssseg6e64.v Vector strided store 6 elements of 64 bits

vssseg6e8.v Vector segmented store 6 elements of 8 bits with stride

vssseg7e16.v Vector segmented store 7 elements of 16 bits with stride

vssseg7e32.v Vector segmented store 7 elements of 32 bits with stride

vssseg7e64.v Vector strided store 7 elements of 64 bits

vssseg7e8.v Vector segmented store 7 elements of 8 bits with stride

vssseg8e16.v Vector segmented store 8 elements of 16 bits with stride

vssseg8e32.v Vector segmented store 8 elements of 32 bits with stride

vssseg8e64.v Vector segmented store 8 elements of 64 bits with stride

vssseg8e8.v Vector strided store 8 elements of 8 bits

vssub.vv Vector subtraction

vssub.vx Vector subtraction with scalar

vssubu.vv Vector unsigned subtraction

vssubu.vx Vector unsigned subtraction with scalar

vsub.vv Vector-vector integer subtraction

vsub.vx Vector-scalar integer subtraction

vsuxei16.v Vector unordered store 1 element of 16 bits with index

vsuxei32.v Vector unordered store 1 element of 32 bits with index

vsuxei64.v Vector unordered store 1 element of 64 bits with index

vsuxei8.v Vector unordered store 1 element of 8 bits with index

vsuxseg2ei16.v Vector unordered store 2 elements of 16 bits with index

vsuxseg2ei32.v Vector unordered store 2 elements of 32 bits with index

vsuxseg2ei64.v Vector unordered store 2 elements of 64 bits with index

vsuxseg2ei8.v Vector unordered store 2 elements of 8 bits with index

vsuxseg3ei16.v Vector unordered store 3 elements of 16 bits with index

vsuxseg3ei32.v Vector unordered store 3 elements of 32 bits with index

vsuxseg3ei64.v Vector unordered store 3 elements of 64 bits with index

vsuxseg3ei8.v Vector unordered store 3 elements of 8 bits with index

vsuxseg4ei16.v Vector unordered store 4 elements of 16 bits with index

vsuxseg4ei32.v Vector unordered store 4 elements of 32 bits with index

vsuxseg4ei64.v Vector unordered store 4 elements of 64 bits with index

vsuxseg4ei8.v Vector unordered store 4 elements of 8 bits with index

vsuxseg5ei16.v Vector unordered store 5 elements of 16 bits with index

vsuxseg5ei32.v Vector unordered store 5 elements of 32 bits with index

vsuxseg5ei64.v Vector unordered store 5 elements of 64 bits with index

vsuxseg5ei8.v Vector unordered store 5 elements of 8 bits with index

vsuxseg6ei16.v Vector unordered store 6 elements of 16 bits with index

vsuxseg6ei32.v Vector unordered store 6 elements of 32 bits with index

vsuxseg6ei64.v Vector unordered store 6 elements of 64 bits with index

vsuxseg6ei8.v Vector unordered store 6 elements of 8 bits with index

vsuxseg7ei16.v Vector unordered store 7 elements of 16 bits with index

vsuxseg7ei32.v Vector unordered store 7 elements of 32 bits with index

vsuxseg7ei64.v Vector unordered store 7 elements of 64 bits with index

vsuxseg7ei8.v Vector unordered store 7 elements of 8 bits with index

vsuxseg8ei16.v Vector unordered store 8 elements of 16 bits with index

vsuxseg8ei32.v Vector unordered store 8 elements of 32 bits with index

vsuxseg8ei64.v Vector unordered store 8 elements of 64 bits with index

vsuxseg8ei8.v Vector unordered store 8 elements of 8 bits with index

vwadd.vv Vector widening unsigned addition

vwadd.vx Vector widening unsigned addition with scalar

vwadd.wv No synopsis available

vwadd.wx No synopsis available

vwaddu.vv Vector widening signed addition

vwaddu.vx Vector widening signed addition with scalar

vwaddu.wv No synopsis available

vwaddu.wx No synopsis available

vwmacc.vv Vector widening multiply-add

vwmacc.vx Vector widening multiply-add with scalar

vwmaccsu.vv Vector widening signed-unsigned multiply-add

vwmaccsu.vx Vector widening signed-unsigned multiply-add with scalar

vwmaccu.vv Vector widening unsigned multiply-add

vwmaccu.vx Vector widening unsigned multiply-add with scalar

vwmaccus.vx Vector widening unsigned multiply-add with scalar, signed

vwmul.vv Vector widening signed multiplication

vwmul.vx Vector widening signed multiplication with scalar

vwmulsu.vv Vector widening signed-unsigned multiplication

vwmulsu.vx Vector widening signed-unsigned multiplication with scalar

vwmulu.vv Vector widening unsigned multiplication

vwmulu.vx Vector widening unsigned multiplication with scalar

vwredsum.vs No synopsis available

vwredsumu.vs No synopsis available

vwsub.vv Vector widening signed subtraction

vwsub.vx Vector widening signed subtraction with scalar

vwsub.wv No synopsis available

vwsub.wx No synopsis available

vwsubu.vv Vector widening unsigned subtraction

vwsubu.vx Vector widening unsigned subtraction with scalar

vwsubu.wv No synopsis available

vwsubu.wx No synopsis available

vxor.vi Vector bitwise XOR with immediate

vxor.vv Vector-vector bitwise XOR

vxor.vx Vector bitwise XOR with scalar

vzext.vf2 Vector zero-extend by factor of 2

vzext.vf4 Vector zero-extend by factor of 4

vzext.vf8 Vector zero-extend by factor of 8

amoadd.d.aq Atomic fetch-and-add doubleword (acquire)

amoadd.d.aqrl Atomic fetch-and-add doubleword (acquire-release)

amoadd.d.rl Atomic fetch-and-add doubleword (release)

amoadd.d Atomic fetch-and-add doubleword

amoadd.w.aq Atomic fetch-and-add word (acquire)

amoadd.w.aqrl Atomic fetch-and-add word (acquire-release)

amoadd.w.rl Atomic fetch-and-add word (release)

amoadd.w Atomic fetch-and-add word

amoand.d.aq Atomic fetch-and-and doubleword (acquire)

amoand.d.aqrl Atomic fetch-and-and doubleword (acquire-release)

amoand.d.rl Atomic fetch-and-and doubleword (release)

amoand.d Atomic fetch-and-and doubleword

amoand.w.aq Atomic fetch-and-and word (acquire)

amoand.w.aqrl Atomic fetch-and-and word (acquire-release)

amoand.w.rl Atomic fetch-and-and word (release)

amoand.w Atomic fetch-and-and word

amomax.d.aq Atomic MAX doubleword (acquire)

amomax.d.aqrl Atomic MAX doubleword (acquire-release)

amomax.d.rl Atomic MAX doubleword (release)

amomax.d Atomic MAX doubleword

amomax.w.aq Atomic MAX word (acquire)

amomax.w.aqrl Atomic MAX word (acquire-release)

amomax.w.rl Atomic MAX word (release)

amomax.w Atomic MAX word

amomaxu.d.aq Atomic MAX unsigned doubleword (acquire)

amomaxu.d.aqrl Atomic MAX unsigned doubleword (acquire-release)

amomaxu.d.rl Atomic MAX unsigned doubleword (release)

amomaxu.d Atomic MAX unsigned doubleword

amomaxu.w.aq Atomic MAX unsigned word (acquire)

amomaxu.w.aqrl Atomic MAX unsigned word (acquire-release)

amomaxu.w.rl Atomic MAX unsigned word (release)

amomaxu.w Atomic MAX unsigned word

amomin.d.aq Atomic MIN doubleword (acquire)

amomin.d.aqrl Atomic MIN doubleword (acquire-release)

amomin.d.rl Atomic MIN doubleword (release)

amomin.d Atomic MIN doubleword

amomin.w.aq Atomic MIN word (acquire)

amomin.w.aqrl Atomic MIN word (acquire-release)

amomin.w.rl Atomic MIN word (release)

amomin.w Atomic MIN word

amominu.d.aq Atomic MIN unsigned doubleword (acquire)

amominu.d.aqrl Atomic MIN unsigned doubleword (acquire-release)

amominu.d.rl Atomic MIN unsigned doubleword (release)

amominu.d Atomic MIN unsigned doubleword

amominu.w.aq Atomic MIN unsigned word (acquire)

amominu.w.aqrl Atomic MIN unsigned word (acquire-release)

amominu.w.rl Atomic MIN unsigned word (release)

amominu.w Atomic MIN unsigned word

amoor.d.aq Atomic fetch-and-or doubleword (acquire)

amoor.d.aqrl Atomic fetch-and-or doubleword (acquire-release)

amoor.d.rl Atomic fetch-and-or doubleword (release)

amoor.d Atomic fetch-and-or doubleword

amoor.w.aq Atomic fetch-and-or word (acquire)

amoor.w.aqrl Atomic fetch-and-or word (acquire-release)

amoor.w.rl Atomic fetch-and-or word (release)

amoor.w Atomic fetch-and-or word

amoswap.d.aq Atomic SWAP doubleword (acquire)

amoswap.d.aqrl Atomic SWAP doubleword (acquire-release)

amoswap.d.rl Atomic SWAP doubleword (release)

amoswap.d Atomic SWAP doubleword

amoswap.w.aq Atomic SWAP word (acquire)

amoswap.w.aqrl Atomic SWAP word (acquire-release)

amoswap.w.rl Atomic SWAP word (release)

amoswap.w Atomic SWAP word

amoxor.d.aq Atomic fetch-and-xor doubleword (acquire)

amoxor.d.aqrl Atomic fetch-and-xor doubleword (acquire-release)

amoxor.d.rl Atomic fetch-and-xor doubleword (release)

amoxor.d Atomic fetch-and-xor doubleword

amoxor.w.aq Atomic fetch-and-xor word (acquire)

amoxor.w.aqrl Atomic fetch-and-xor word (acquire-release)

amoxor.w.rl Atomic fetch-and-xor word (release)

amoxor.w Atomic fetch-and-xor word

lr.d Load reserved doubleword

lr.w Load reserved word

sc.d Store conditional doubleword

sc.w Store conditional word

add.uw Add unsigned word

sh1add.uw Shift unsigned word left by 1 and add

sh1add Shift left by 1 and add

sh2add.uw Shift unsigned word left by 2 and add

sh2add Shift left by 2 and add

sh3add.uw Shift unsigned word left by 3 and add

sh3add Shift left by 3 and add

slli.uw Shift left unsigned word (Immediate)

clz Count leading zero bits

clzw Count leading zero bits in word

cpop Count set bits

cpopw Count set bits in word

ctz Count trailing zero bits

ctzw Count trailing zero bits in word

max Maximum

maxu Unsigned maximum

min Minimum

minu Unsigned minimum

orc.b Bitware OR-combine, byte granule

sext.b Sign-extend byte

sext.h Sign-extend halfword

zext.h Zero-extend halfword

bclr Single-Bit clear (Register)

bclri Single-Bit clear (Immediate)

bext Single-Bit extract (Register)

bexti Single-Bit extract (Immediate)

binv Single-Bit invert (Register)

binvi Single-Bit invert (Immediate)

bset Single-Bit set (Register)

bseti Single-Bit set (Immediate)

c.fld Load double-precision

c.fldsp Load doubleword into floating-point register from stack

c.fsd Store double-precision

c.fsdsp Store double-precision value to stack

cbo.clean Cache Block Clean

cbo.flush Cache Block Flush

cbo.inval Cache Block Invalidate

cbo.zero Cache Block Zero

csrrc Atomic Read and Clear Bits in CSR

csrrci Atomic Read and Clear Bits in CSR with Immediate

csrrs Atomic Read and Set Bits in CSR

csrrsi Atomic Read and Set Bits in CSR with Immediate

csrrw Atomic Read/Write CSR

csrrwi Atomic Read/Write CSR Immediate