sip

Supervisor Interrupt Pending

A restricted view of the interrupt pending bits in mip.

Hypervisor-related interrupts (VS-mode interrupts and Supervisor Guest interrupts) are not reflected in sip even though those interrupts can be taken in HS-mode. Instead, they are reported through hip.

Attributes

CSR Address	0x144
Defining extension	S
Length	64-bit
Privilege Mode	S

CSR Address

0x144

Defining extension

Length

64-bit

Privilege Mode

Format

Figure 1. sip format

Field Summary

Name Location Type Reset Value

Name	Location	Type	Reset Value
`SSIP`	1	RW-R	UNDEFINED_LEGAL
`STIP`	5	RO-H	UNDEFINED_LEGAL
`SEIP`	9	RO-H	UNDEFINED_LEGAL
`LCOFIP`	13	RW-RH	UNDEFINED_LEGAL

SSIP

RW-R

UNDEFINED_LEGAL

STIP

RO-H

UNDEFINED_LEGAL

SEIP

RO-H

UNDEFINED_LEGAL

LCOFIP

RW-RH

UNDEFINED_LEGAL

Fields

`SSIP`

Location

sip[1]

Description

Supervisor Software Interrupt Pending

Reports the current pending state of an (H)S-mode software interrupt.

When Supervisor Software Interrupts are not delegated to (H)S-mode (mideleg.SSI is clear), sip.SSIP is read-only 0.

Otherwise, sip.SSIP is an alias of mip.SSIP.

When using AIA/IMSIC, IPIs are expected to be delivered as external interrupts and SSIP is not backed by any hardware update (aside from any aliasing effects).

However, SSIP is still writable by S-mode software and, when written, can be used to generate an S-mode Software Interrupt.

Since it is an alias, writes to sip.SSIP are also be reflected in mip.SSIP and mvip.SSIP.

Aliases:

mip.SSIP when mideleg.SSI is set
mvip.SSIP when mideleg.SSI is set

To summarize:

mideleg.SSI

sip.SSIP behavior +

read-only 0

writable alias of mip.SSIP and mvip.SSIP

Type

RW-R	Read-Write Restricted Field is writable by software. Only certain values are legal. Writing an illegal value into the field is ignored, and the field retains its prior state.

Reset value

UNDEFINED_LEGAL

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (CSR[mideleg].SSI == 1'b1) {
  CSR[mip].SSIP = csr_value.SSIP;
  return csr_value.SSIP;
}
return 1'b0;

`STIP`

Location

sip[5]

Description

Supervisor Timer Interrupt Pending

Reports the current pending state of an (H)S-mode timer interrupt.

When Supervisor Timer Interrupts are not delegated to (H)S-mode (i.e., mideleg.STI is clear), sip.STIP is read-only 0.

Otherwise, sip.STIP is a read-only view of mip.STIP.

Aliases:

mip.STIP when mideleg.STI is set
mvip.STIP when mideleg.SSI is set and menvcfg.STCE is clear.

To summarize:

mideleg.STI

sip.STIP behavior +

read-only 0

read-only alias of mip.STIP (and mvip.STIP when menvcfg.STCE is clear)

Type

RO-H	Read-Only with Hardware update Writes are ignored. Reads reflect a value dynamically generated by hardware.

Reset value: UNDEFINED_LEGAL

`SEIP`

Location: sip[9]
Description: Supervisor External Interrupt Pending

Reports the current pending state of an (H)S-mode external interrupt.

When Supervisor External Interrupts are not delegated to (H)S-mode (i.e., mideleg.SEI is clear), sip.SEIP is read-only 0.

Otherwise, sip.SEIP is a read-only view of mip.SEIP.

To summarize:

mideleg.SEI

sip.SEIP behavior +

read-only 0

read-only alias of mip.SEIP

Type

RO-H	Read-Only with Hardware update Writes are ignored. Reads reflect a value dynamically generated by hardware.

Reset value: UNDEFINED_LEGAL

`LCOFIP`

Location: sip[13]
Description: Local Counter Overflow Interrupt pending

Reports the current pending state of a Local Counter Overflow interrupt.

When Local Counter Overflow interrupts are not delegated to (H)S-mode (i.e., mideleg.LCOFI is clear), sip.LCOFIP is read-only 0.

Otherwise, sip.LCOFIP is an alias of mip.LCOFIP.

Software writes 0 to sip.LCOFIP to clear the pending interrupt.

To summarize:

mideleg.LCOFI

sip.LCOFIP behavior +

read-only 0

writable alias of mip.LCOFIP (and vsip.LCOFIP when hideleg.LCOFI is set)

Type

RW-RH

Read-Write Restricted with Hardware update

Field is writable by software. Only certain values are legal. Writing an illegal value into the field is ignored, such that the field retains its prior state. Hardware also updates the field without an explicit software write.)

Reset value

UNDEFINED_LEGAL

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (CSR[mideleg].LCOFI == 1'b1) {
  CSR[mip].LCOFIP = csr_value.LCOFIP;
  return csr_value.LCOFIP;
}
return 1'b0;

Software read

This CSR may return a value that is different from what is stored in hardware.

Pruned
Original

return $bits(CSR[CSR[mip]]) & $bits(CSR[CSR[mideleg]]);

return $bits(CSR[CSR[mip]]) & $bits(CSR[CSR[mideleg]]);