vmv.v.i

Vector move immediate to vector register

This instruction is defined by:

Encoding

Synopsis

Copies a sign-extended 5-bit immediate value to all body elements of the destination vector register group. This is an unmasked instruction (vm=1).

The 5-bit immediate (simm[4:0]) is sign-extended to SEW bits and written to each body element of the destination vector register group (elements from vstart to vl-1). Prestart elements (indices less than vstart) are unchanged. Tail elements (indices >= vl) are handled according to the tail agnostic/undisturbed policy.

Access

M	HS	U	VS	VU
Always	Always	Always	Always	Always

Always

Decode Variables

signed Bits<5> imm = sext($encoding[19:15], 5);
Bits<5> vd = $encoding[11:7];

Execution

Pruned, XLEN == 64
Original

VectorState state = vector_state();
VectorLmulType lmul_type = state.lmul_type;
XReg vlen = 17'128;
XReg vlmax;
if (lmul_type == VectorLmulType::Multiply) {
  vlmax = (64'128 << state.log2_lmul) >> state.log2_sew;
} else {
  vlmax = (64'128 >> state.log2_lmul) >> state.log2_sew;
}
XReg sext_imm = $signed(imm);
for (U32 i = CSR[vstart].VALUE; i < CSR[vl].VALUE; i++) {
  U32 start_bit_pos = i * state.sew;
  U32 end_bit_pos = start_bit_pos + state.sew - 1;
  V[vd][end_bit_pos:start_bit_pos] = sext_imm[state.sew - 1:0];
}
CSR[vstart].VALUE = 0;

VectorState state = vector_state();
VectorLmulType lmul_type = state.lmul_type;
XReg vlen = VLEN;
XReg vlmax;
if (lmul_type == VectorLmulType::Multiply) {
  vlmax = (vlen << state.log2_lmul) >> state.log2_sew;
} else {
  vlmax = (vlen >> state.log2_lmul) >> state.log2_sew;
}
XReg sext_imm = $signed(imm);
for (U32 i = CSR[vstart].VALUE; i < CSR[vl].VALUE; i++) {
  U32 start_bit_pos = i * state.sew;
  U32 end_bit_pos = start_bit_pos + state.sew - 1;
  V[vd][end_bit_pos:start_bit_pos] = sext_imm[state.sew - 1:0];
}
CSR[vstart].VALUE = 0;