vabd.vx

Vector Single-Width Signed Integer Absolute Difference with Scalar

This instruction is defined by:

Encoding

Synopsis

Computes the element-wise absolute difference of signed integer operands from vector register vs2 and scalar register xs1, and writes the SEW-bit results to vd according to mask vm. The scalar is sign-extended or truncated to SEW.

Supports SEW of 8, 16, and 32, and SEW of 64 when Zve64x is implemented.

Access

M	HS	U	VS	VU
Always	Always	Always	Always	Always

Always

Decode Variables

Bits<1> vm = $encoding[25];
Bits<5> vs2 = $encoding[24:20];
Bits<5> xs1 = $encoding[19:15];
Bits<5> vd = $encoding[11:7];

Execution

Pruned, XLEN == 64
Original

VectorState state = vector_state();
VectorLmulType lmul_type = state.lmul_type;
XReg vlen = 17'128;
XReg vlmax;
if (lmul_type == VectorLmulType::Multiply) {
  vlmax = (64'128 << state.log2_lmul) >> state.log2_sew;
} else {
  vlmax = (64'128 >> state.log2_lmul) >> state.log2_sew;
}
Bits<64> scalar = $signed(X[xs1]);
for (U32 i = CSR[vstart].VALUE; i < CSR[vl].VALUE; i) {
  U32 start_bit_pos = i * state.sew;
  U32 end_bit_pos = start_bit_pos pass:[+] state.sew - 1;
  if pass:[(]vm == 1'b1 || V[0][i:i] == 1'b1) {
    if pass:[(]$signed(V[vs2][end_bit_pos:start_bit_pos]) >= $signed(++scalar[state.sew - 1:0])) {
      V[vd][end_bit_pos:start_bit_pos] = V[vs2][end_bit_pos:start_bit_pos] - scalar[state.sew - 1:0];
    } else {
      V[vd][end_bit_pos:start_bit_pos] = scalar[state.sew - 1:0] - V[vs2][end_bit_pos:start_bit_pos];
    }
  }
}
CSR[vstart].VALUE = 0;

VectorState state = vector_state();
VectorLmulType lmul_type = state.lmul_type;
XReg vlen = VLEN;
XReg vlmax;
if (lmul_type == VectorLmulType::Multiply) {
  vlmax = (vlen << state.log2_lmul) >> state.log2_sew;
} else {
  vlmax = (vlen >> state.log2_lmul) >> state.log2_sew;
}
Bits<64> scalar = $signed(X[xs1]);
for (U32 i = CSR[vstart].VALUE; i < CSR[vl].VALUE; i) {
  U32 start_bit_pos = i * state.sew;
  U32 end_bit_pos = start_bit_pos pass:[+] state.sew - 1;
  if pass:[(]vm == 1'b1 || V[0][i:i] == 1'b1) {
    if pass:[(]$signed(V[vs2][end_bit_pos:start_bit_pos]) >= $signed(++scalar[state.sew - 1:0])) {
      V[vd][end_bit_pos:start_bit_pos] = V[vs2][end_bit_pos:start_bit_pos] - scalar[state.sew - 1:0];
    } else {
      V[vd][end_bit_pos:start_bit_pos] = scalar[state.sew - 1:0] - V[vs2][end_bit_pos:start_bit_pos];
    }
  }
}
CSR[vstart].VALUE = 0;