vssseg6e64.v

Vector strided store 6 elements of 64 bits

This instruction is defined by:

Encoding

Synopsis

Stores 6 segments of 64-bit elements from vector register vs2 to memory starting at address in xs1 register with stride, using vector mask vm. The effective element width is 64 bits.

Access

M	HS	U	VS	VU
Always	Always	Always	Always	Always

Always

Decode Variables

Bits<1> vm = $encoding[25];
Bits<5> xs2 = $encoding[24:20];
Bits<5> xs1 = $encoding[19:15];
Bits<5> vs3 = $encoding[11:7];

Execution

Pruned, XLEN == 64
Original