fleq.s

Floating-Point Less Than or Equal Quiet Single-Precision

This instruction is defined by:

Encoding

Synopsis

The fleq.s instruction is defined like the fle.s instruction, except that quiet NaN inputs do not cause the invalid operation exception flag to be set.

Access

M	HS	U	VS	VU
Always	Always	Always	Always	Always

Always

Decode Variables

Bits<5> fs2 = $encoding[24:20];
Bits<5> fs1 = $encoding[19:15];
Bits<5> xd = $encoding[11:7];

Execution

Pruned, XLEN == 64
Original

check_f_ok($encoding);
Bits<32> sp_value_a = F[fs1][31:0];
Bits<32> sp_value_b = F[fs2][31:0];
if (is_sp_nan?(sp_value_a) || is_sp_nan?(sp_value_b)) {
  if (is_sp_signaling_nan?(sp_value_a) || is_sp_signaling_nan?(sp_value_b)) {
    set_fp_flag(FpFlag::NV);
  }
  X[xd] = 0;
} else {
  Boolean sign_a = sp_value_a[31] == 1;
  Boolean sign_b = sp_value_b[31] == 1;
  Boolean a_eq_b = (sp_value_a == sp_value_b) || sp_value_a | sp_value_b)[30:0] == 0);   Boolean a_lt_b;   if (sign_a != sign_b) {     a_lt_b = sign_a && ((sp_value_a[30:0] | sp_value_b[30:0]) != 0);   } else {     a_lt_b = (sp_value_a != sp_value_b) && (sign_a != (sp_value_a < sp_value_b;
  }
  X[xd] = (a_lt_b || a_eq_b) ? 1 : 0;
}

check_f_ok($encoding);
Bits<32> sp_value_a = F[fs1][31:0];
Bits<32> sp_value_b = F[fs2][31:0];
if (is_sp_nan?(sp_value_a) || is_sp_nan?(sp_value_b)) {
  if (is_sp_signaling_nan?(sp_value_a) || is_sp_signaling_nan?(sp_value_b)) {
    set_fp_flag(FpFlag::NV);
  }
  X[xd] = 0;
} else {
  Boolean sign_a = sp_value_a[31] == 1;
  Boolean sign_b = sp_value_b[31] == 1;
  Boolean a_eq_b = (sp_value_a == sp_value_b) || sp_value_a | sp_value_b)[30:0] == 0);   Boolean a_lt_b;   if (sign_a != sign_b) {     a_lt_b = sign_a && ((sp_value_a[30:0] | sp_value_b[30:0]) != 0);   } else {     a_lt_b = (sp_value_a != sp_value_b) && (sign_a != (sp_value_a < sp_value_b;
  }
  X[xd] = (a_lt_b || a_eq_b) ? 1 : 0;
}

Exceptions

This instruction may result in the following synchronous exceptions:

IllegalInstruction