mhpmcounter3

Machine Hardware Performance Counter 3

Programmable hardware performance counter.

The hpmcounter3 CSR is a read-only shadow of this CSR. Access to hpmcounter3 is controlled with mcounteren.HPM3 , scounteren.HPM3 , and hcounteren.HPM3 as follows:

mcounteren.HPM3	scounteren.HPM3	hcounteren.HPM3	hpmcounter3 behavior
S-mode	U-mode	VS-mode	VU-mode
0	-	-	`IllegalInstruction`	`IllegalInstruction`	`IllegalInstruction`	`IllegalInstruction`
1	0	0	read-only	`IllegalInstruction`	`VirtualInstruction`	`VirtualInstruction`
1	1	0	read-only	read-only	`VirtualInstruction`	`VirtualInstruction`
1	0	1	read-only	`IllegalInstruction`	read-only	`VirtualInstruction`
1	1	1	read-only	read-only	read-only	read-only

mcounteren.HPM3

scounteren.HPM3

hcounteren.HPM3

hpmcounter3 behavior

S-mode

U-mode

VS-mode

VU-mode

IllegalInstruction

read-only

IllegalInstruction

VirtualInstruction

read-only

VirtualInstruction

read-only

IllegalInstruction

read-only

VirtualInstruction

read-only

Attributes

CSR Address	0xb03
Defining extension	(Sm && `HPM_COUNTER_EN[3]` == true)
Length	64-bit
Privilege Mode	M

CSR Address

0xb03

Defining extension

(Sm && HPM_COUNTER_EN[3] == true)

Length

64-bit

Privilege Mode

Format

Figure 1. mhpmcounter3 format

Field Summary

Name Location Type Reset Value

Name	Location	Type	Reset Value
`COUNT`	63:0	RW-H	UNDEFINED_LEGAL

COUNT

63:0

RW-H

UNDEFINED_LEGAL

Fields

`COUNT`

Location: mhpmcounter3[63:0]
Description

Performance counter for event selected in mhpmevent3.EVENT.

+ Increments every time event occurs unless:

+ * mcountinhibit.HPM3 or its alias scountinhibit.HPM3 is set * mhpmevent3.MINH is set and the current privilege level is M * mhpmevent3.SINH or its alias hpmevent3.SINH is set and the current privilege level is (H)S * mhpmevent3.UINH or its alias hpmevent3.UINH is set and the current privilege level is U * mhpmevent3.VSINH or its alias hpmevent3.VSINH is set and the current privilege level is VS * mhpmevent3.VUINH or its alias hpmevent3.VUINH is set and the current privilege level is VU

Unimplemented performance counter. Must be read-only 0 (access does not cause trap).

Type

RW-H	Read-Write with Hardware update Field is writable by software. Any value that fits in the field is acceptable. Hardware also updates the field without an explicit software write.

Reset value: UNDEFINED_LEGAL

Software read

This CSR may return a value that is different from what is stored in hardware.

Pruned
Original

return read_hpm_counter(3);

if (HPM_COUNTER_EN[3]) {
  return read_hpm_counter(3);
} else {
  return 0;
}