vsaddu.vv

Vector signed addition

This instruction is defined by:

Encoding

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Synopsis

Performs signed addition on elements from vector registers vs2 and vs1 and stores results in vector register vd, using vector mask vm. The operation follows standard signed arithmetic rules.

Access

M HS U VS VU

Always

Always

Always

Always

Always

Decode Variables

Bits<1> vm = $encoding[25];
Bits<5> vs2 = $encoding[24:20];
Bits<5> vs1 = $encoding[19:15];
Bits<5> vd = $encoding[11:7];

Execution

  • Pruned, XLEN == 64

  • Original