vl8re16.v

Vector load 8 elements of 16 bits with register stride

This instruction is defined by:

Encoding

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Synopsis

Loads 8 segments of 16-bit elements from memory starting at address in xs1 register with stride in xs2, using vector mask vm, and stores results in vector register vd. The effective element width is 16 bits.

Access

M HS U VS VU

Always

Always

Always

Always

Always

Decode Variables

Bits<5> xs1 = $encoding[19:15];
Bits<5> vd = $encoding[11:7];

Execution

  • Pruned, XLEN == 64

  • Original