Sm Extension

Implemented Version

1.12.0

Versions

Version 1.11.0

State

ratified

Ratification date

2019-12

Changes

  • Moved Machine spec to Ratified status.

  • Improvements to the description and commentary.

  • Specified which interrupt sources are reserved for standard use.

  • Allocated some synchronous exception causes for custom use.

  • Specified the priority ordering of synchronous exceptions.

  • Added specification that xRET instructions may, but are not required to, clear LR reservations if A extension present.

  • Made the mstatus.MPP field WARL, rather than WLRL.

  • Made the unused xip fields WPRI, rather than WIRI.

  • Made the unused misa fields WARL, rather than WIRI.

  • Rectified an editing error that misdescribed the mechanism by which mstatus is written upon an exception.

  • Described scheme for emulating misaligned AMOs.

  • Specified the behavior of the misa and xepc registers in systems with variable IALIGN.

  • Specified the behavior of writing self-contradictory values to the misa register.

  • Specified contents of CSRs across XLEN modification.

  • Moved PLIC chapter into its own document.
Version 1.12.0

State

ratified

Ratification date

2021-12

Changes

  • Changed MRET to clear mstatus.MPRV when leaving M-mode.

  • Relaxed I/O regions have been specified to follow RVWMO. The previous specification implied that PPO rules other than fences and acquire/release annotations did not apply.

  • Constrained the LR/SC reservation set size and shape when using page-based virtual memory.

  • PMP changes require an SFENCE.VMA on any hart that implements page-based virtual memory, even if VM is not currently enabled.

  • Removed the N extension.

  • Defined the mandatory RV32-only CSR mstatush, which contains most of the same fields as the upper 32 bits of RV64’s mstatus.

  • Defined the mandatory CSR mconfigptr, which if nonzero contains the address of a configuration data structure.

  • Defined mseccfg and mseccfgh CSRs, which control the machine’s security configuration.

  • Defined menvcfg CSR (and RV32-only menvcfgh), which control various characteristics of the execution environment.

  • Designated part of SYSTEM major opcode for custom use.

  • Permitted the unconditional delegation of less-privileged interrupts.

  • Added optional big-endian and bi-endian support.

  • Made priority of load/store/AMO address-misaligned exceptions implementation-defined relative to load/store/AMO page-fault and access-fault exceptions.

  • Software breakpoint exceptions are permitted to write either 0 or the pc to xtval.

  • Specified relaxed constraints for implicit reads of non-idempotent regions.
Version 1.13.0

State

frozen

Changes

  • Redefined misa.MXL to be read-only, making MXLEN a constant.

  • Defined the misa.B field to reflect that the B extension has been implemented.

  • Defined the misa.V field to reflect that the V extension has been implemented.

  • Defined the RV32-only medelegh CSR.

  • Defined the misaligned atomicity granule PMA, superseding the proposed Zam extension.

  • Defined hardware error and software check exception codes.

  • Specified synchronization requirements when changing the PBMTE fields in menvcfg and henvcfg.

  • Exposed count-overflow interrupts to VS-mode via the Shlcofideleg extension.

  • Relaxed behavior of some HINTs when MXLEN > XLEN.

  • Transliterated the document from LaTeX into AsciiDoc.

  • Included all ratified extensions through March 2024.

  • Clarified that "platform- or custom-use" interrupts are actually "platform-use interrupts", where the platform can choose to make some custom.

  • Clarified semantics of explicit accesses to CSRs wider than XLEN bits.

  • Clarified that MXLEN≥SXLEN.

  • Clarified that WFI is not a HINT instruction.

  • Clarified that, for a given exception cause, xtval might sometimes be set to a nonzero value but sometimes not.

  • Clarified exception behavior of unimplemented or inaccessible CSRs.

  • Replaced the concept of vacant memory regions with inaccessible memory or I/O regions.

  • Clarified that timer and count-overflow interrupts' arrival in interrupt-pending registers is not immediate.

  • Clarified that MXR affects only explicit memory accesses.

Synopsis

This chapter describes the machine-level operations available in machine-mode (M-mode), which is the highest privilege mode in a RISC-V hart. M-mode is used for low-level access to a hardware platform and is the first mode entered at reset. M-mode can also be used to implement features that are too difficult or expensive to implement in hardware directly. The RISC-V machine-level ISA contains a common core that is extended depending on which other privilege levels are supported and other details of the hardware implementation. This chapter describes the RISC-V machine-level architecture, which contains a common core that is used with various supervisor-level address translation and protection schemes.

Instructions

The following instructions are added by this extension in the example_rv64_with_overlay configuration:

mret

Machine-mode Return from Trap

wfi

Wait for interrupt

Parameters

This extension has the following implementation options:

HPM_COUNTER_EN

Whether each HPM counter is implemented in hardware.

HPM_COUNTER_EN[n] being false means hpmcounter<n>/mhpmcounter<n> and the corresponding mhpmevent<n> are not implemented and are hardwired read-only zero. (It does not mean the counter is implemented but currently stopped from counting; that is a separate, run-time concept controlled by mcountinhibit.)

There is one entry for each hpmcounter, indexed 0-31.

Indices 0-2 must be false: they are placeholders for the three counters (cycle/mcycle (CY), time ™, and instret/minstret (IR)) whose implementation this parameter does not control. These counters are associated with indexes 0, 1, and 2. The rest of the HPM counters logically follow at indexes 3-31. Index 3 in HPM_COUNTER_EN corresponds to mhpmcounter3. Index 31 in HPM_COUNTER_EN corresponds to mhpmcounter31.

MARCHID_IMPLEMENTED

  • false: marchid is not implemented, and must be read-only-0

  • true: marchid is implemented, and the value is determined by ARCH_ID_VALUE

MCOUNTENABLE_EN

Indicates which counters can be delegated via mcounteren.

An unimplemented counter cannot be specified, i.e., if HPM_COUNTER_EN[3] is false, it would be illegal to set MCOUNTENABLE_EN[3] to true.

MCOUNTENABLE_EN[0:2] must all be false if Zicntr is not implemented. MCOUNTENABLE_EN[3:31] must all be false if Zihpm is not implemented.

MCOUNTINHIBIT_IMPLEMENTED

Options:

true

The mcountinhibit CSR is implemented and can be accessed in M-mode.

false

The mcountinhibit CSR is not implemented. Accessing the CSR will cause an IllegalInstruction trap or enter an unpredictable state, depending on TRAP_ON_UNIMPLEMENTED_CSR.

MIMPID_IMPLEMENTED

  • false: mimpid is not implemented, and must be read-only-0

  • true: mimpid is implemented, and the value is determined by IMP_ID_VALUE

MISALIGNED_LDST

Does the implementation perform non-atomic misaligned loads and stores to main memory (does not affect misaligned support to device memory)? If not, the implementation always throws a misaligned exception.

MISALIGNED_LDST_EXCEPTION_PRIORITY

The relative priority of a load/store/AMO exception vs. load/store/AMO page-fault or access-fault exceptions.

May be one of:

low

Misaligned load/store/AMO exceptions are always lower priority than load/store/AMO page-fault and access-fault exceptions.

high

Misaligned load/store/AMO exceptions are always higher priority than load/store/AMO page-fault and access-fault exceptions.

MISALIGNED_LDST_EXCEPTION_PRIORITY cannot be "high" when MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE is non-zero, since the atomicity of an access cannot be determined in that case until after address translation.

MISA_CSR_IMPLEMENTED

Options:

true

The misa CSR returns a non-zero value.

false

The misa CSR is read-only-0.

MTVAL_WIDTH

The number of implemented bits in the mtval CSR. This is the CSR that may be written when a trap is taken into M-mode with exception-specific information to assist software in handling the trap (e.g., address associated with exception).

Must be greater than or equal to max(PHYS_ADDR_WIDTH, VA_SIZE)

MTVEC_ACCESS

Options:

ro

mtvec is read-only.

rw

mtvec is read-write, but may not accept all values.

MTVEC_ILLEGAL_WRITE_BEHAVIOR

Options:

retain

When either mtvec.MODE or mtvec.BASE is illegal, mtvec will retain its current value

custom

When either mtvec.MODE or mtvec.BASE is illegal, mtvec will obtain an unpredictable value

Other values may be added over time once other common behaviors are identified.

MTVEC_MODES

Options:

0

Direct; All traps set pc to mtvec.BASE

1

Vectored; Asynchronous interrupts set pc to mtvec.BASE + 4 x cause.

If only one mode is given, mtvec.MODE is assumed to be read-only with that value. Otherwise, mtvec.MODE is read-write.

MXLEN

XLEN in machine mode, specified in bits

M_MODE_ENDIANNESS

Options:

little

M-mode data is always little endian

big

M-mode data is always big endian

dynamic

M-mode data can be either little or big endian, depending on the CSR field mstatus.MBE
NUM_PMP_ENTRIES

Number of implemented PMP entries.

The architecture mandates that the number of implemented PMP registers must appear to be 0, 16, or 64, so NUM_PMP_ENTRIES must be one of those values. It directly determines which PMP registers exist: pmpaddr0-pmpaddr<N-1> and their corresponding pmpNcfg fields are implemented, and the rest are not. Accessing an unimplemented PMP register causes an IllegalInstruction when TRAP_ON_UNIMPLEMENTED_CSR is true.

pmpcfgN for an odd N never exists when XLEN == 64.

An implemented entry may still be read-only zero (but will never cause an exception). The number of entries that are actually usable is given by NUM_USABLE_PMP_ENTRIES.

PHYS_ADDR_WIDTH

Implementation-defined size of the physical address space.

PMA_GRANULARITY

Generally, for systems with an MMU, should not be smaller than 12, as that would preclude caching PMA results in the TLB along with virtual memory translations

PRECISE_SYNCHRONOUS_EXCEPTIONS

If false, any exception not otherwise mandated to precise (e.g., PMP violation) will cause execution to enter an unpredictable state.

REPORT_ENCODING_IN_MTVAL_ON_ILLEGAL_INSTRUCTION

Options:

  • true: mtval is written with the encoding of an instruction causing an IllegalInstruction exception

  • false: mtval is written with 0 when an instruction causes an IllegalInstruction exception.

REPORT_VA_IN_MTVAL_ON_BREAKPOINT

Options:

  • true: mtval is written with the virtual PC of an EBREAK instruction (same information as mepc).

  • false: mtval is written with 0 on an EBREAK instruction.

Regardless, mtval is always written with a virtual PC when an external breakpoint is generated

REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT

Options:

  • true: mtval is written with the virtual address of a fetch causing the access fault

  • false: mtval is written with 0 when a fetch causes an access fault

REPORT_VA_IN_MTVAL_ON_INSTRUCTION_MISALIGNED

Options:

  • true: mtval is written with the virtual address of a trapping misaligned fetch

  • false: mtval is written with 0 when a misaligned fetch traps

REPORT_VA_IN_MTVAL_ON_LOAD_ACCESS_FAULT

Options:

  • true: mtval is written with the virtual address of a load causing the access fault

  • false: mtval is written with 0 when a load causes an access fault

REPORT_VA_IN_MTVAL_ON_LOAD_MISALIGNED

Options:

  • true: mtval is written with the virtual address of a trapping misaligned load.

  • false: mtval is written with 0 when a misaligned load traps.

REPORT_VA_IN_MTVAL_ON_STORE_AMO_ACCESS_FAULT

Options:

  • true: mtval is written with the virtual address of a store or AMO causing the access fault

  • false: mtval is written with 0 when a store or AMO causes an access fault

REPORT_VA_IN_MTVAL_ON_STORE_AMO_MISALIGNED

Options:

  • true: mtval is written with the virtual address of a trapping misaligned store or AMO.

  • false: mtval is written with 0 when a misaligned store or AMO traps.

TRAP_ON_EBREAK

The spec states that implementations may handle EBREAKs transparently without raising a trap, in which case the EEI must provide a builtin.

TRAP_ON_ECALL_FROM_M

The spec states that implementations may handle ECALLs transparently without raising a trap, in which case the EEI must provide a builtin.

TRAP_ON_ILLEGAL_WLRL

Options:

  • true: Writing an illegal value to a WLRL CSR field will cause an IllegalInstruction exception.

  • false: Writing an illegal value to a WLRL CSR field causes unpredictable behavior.

TRAP_ON_RESERVED_INSTRUCTION

Options:

  • true: Fetching an unimplemented and/or undefined instruction from the standard/reserved opcode space will cause an IllegalInstruction exception.

  • false: Fetching an unimplemented and/or undefined instruction from the standard/reserved opcose space causes unpredictable behavior.

TRAP_ON_RESERVED_INSTRUCTION may be false while TRAP_ON_UNIMPLEMENTED_INSTRUCTION is true when a custom instruction is implemented in the standard/reserved opcode space.

TRAP_ON_UNIMPLEMENTED_CSR

Options:

  • true: Accessing an unimplemented CSR (via a Zicsr instruction) will cause an IllegalInstruction exception.

  • false: Accessing an unimplemented CSR (via a Zicsr instruction) will cause unpredictable behavior.

TRAP_ON_UNIMPLEMENTED_INSTRUCTION

Options:

  • true: Fetching an unimplemented instruction will cause an IllegalInstruction exception.

  • false: Fetching an unimplemented instruction causes unpredictable behavior.

An unimplemented instruction is any instruction encoding that is not defined by the implementation. Custom instructions are considered implemented.

VENDOR_ID_BANK

Encodes the number of one-byte continuation codes in the Bank field of mvendorid.

iN JEDEC’s parlance, the bank number is one greater than the number of continuation codes; hence, the mvendorid Bank field encodes a value that is one less than the JEDEC bank number.

VENDOR_ID_OFFSET

Encodes the final byte of a JEDEC manufactor ID, discarding the parity bit.