stimecmp

Supervisor timer compare

Supervisor timer compare register.

When menvcfg.STCE is set, stimecmp is operational and provides supervisor mode with a CSR-based timer interrupt facility.

Attributes

CSR Address

0x14d

Defining extension

Sstc

Length

64-bit

Privilege Mode

S

Format

stimecmp format
Figure 1. stimecmp format

Field Summary

Name Location Type Reset Value

TIME

63:0

RW

UNDEFINED_LEGAL

Fields

TIME

Location

stimecmp[63:0]

Description

Time compare value for supervisor timer interrupts.

Type

RW

Read-Write

Field is writable by software. Any value that fits in the field is acceptable and shall be retained for subsequent reads.
Reset value

UNDEFINED_LEGAL

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (mode() != PrivilegeMode::M) {
  if (true) {
    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
  }
}
return csr_value.TIME;

Software read

This CSR may return a value that is different from what is stored in hardware.

  • Pruned

  • Original

if (mode() != PrivilegeMode::M) {
  if (true) {
    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
  }
}
return CSR[stimecmp].TIME;
if (mode() != PrivilegeMode::M) {
  if (CSR[menvcfg].STCE == 1'b0 || CSR[mcounteren].TM == 1'b0) {
    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
  }
}
return CSR[stimecmp].TIME;