aes64es
AES encrypt final round
This instruction is defined by:
Synopsis
Uses the two 64-bit source registers to represent the entire AES state, and produces half of the next round output, applying the ShiftRows and SubBytes steps.
AES encrypt final round
This instruction is defined by:
Uses the two 64-bit source registers to represent the entire AES state, and produces half of the next round output, applying the ShiftRows and SubBytes steps.