dret

Return from Debug Mode

This instruction is defined by:

Encoding

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Synopsis

Resumes execution after Debug Mode. dret is only legal in Debug Mode; executing it in any other mode raises an Illegal Instruction exception.

When executed in Debug Mode, dret:

  1. Sets the PC to the value in dpc.

  2. Changes the privilege and virtualization mode to those held in dcsr.PRV and dcsr.V.

  3. If the new privilege mode is less privileged than M-mode, clears mstatus.MPRV.

  4. If Smdbltrp is implemented and the new privilege mode is less privileged than M-mode, clears mstatus.MDT.

  5. If Ssdbltrp is implemented and the new privilege mode is U, VS, or VU, clears sstatus; if the new mode is VU, also clears vsstatus.

  6. If Zicfilp is implemented, sets ELP to dcsr.PELP if Zicfilp is enabled (xLPE=1) in the new privilege mode, otherwise to NO_LP_EXPECTED, and then clears dcsr.PELP.

  7. Leaves Debug Mode.

Access

M HS U VS VU

Always

Never

Never

Never

Never

Decode Variables

Execution

  • Pruned, XLEN == 64

  • Original

raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
PrivilegeMode new_mode = PrivilegeMode::M;
if (CSR[dcsr].PRV == 2'b11) {
  new_mode = PrivilegeMode::M;
} else if (CSR[dcsr].PRV == 2'b01) {
  new_mode = PrivilegeMode::S;
  if (implemented?(ExtensionName::H)) {
    if (CSR[dcsr].V == 1'b1) {
      new_mode = PrivilegeMode::VS;
    }
  }
} else if (CSR[dcsr].PRV == 2'b00) {
  new_mode = PrivilegeMode::U;
  if (implemented?(ExtensionName::H)) {
    if (CSR[dcsr].V == 1'b1) {
      new_mode = PrivilegeMode::VU;
    }
  }
} else {
  unpredictable("dcsr.PRV holds a reserved encoding; the hart may resume in any supported privilege mode");
}
if (new_mode != PrivilegeMode::M) {
  if (implemented?(ExtensionName::U)) {
    CSR[mstatus].MPRV = 0;
  }
  if (implemented?(ExtensionName::Smdbltrp)) {
    CSR[mstatus].MDT = 1'b0;
  }
}
if (implemented?(ExtensionName::Zicfilp)) {
  CSR[dcsr].PELP = 1'b0;
}
set_mode(new_mode);
$pc = $bits(CSR[CSR[dpc]]);

Exceptions

This instruction may result in the following synchronous exceptions:

  • IllegalInstruction