vnsrl.wv

Vector narrowing logical shift right

This instruction is defined by:

Encoding

Synopsis

Performs narrowing logical right shift on double-width elements from vector register vs2 by shift amounts from vector register vs1 and stores results in vector register vd, using vector mask vm. The operation fills with zeros and writes a single-width destination.

Access

M	HS	U	VS	VU
Always	Always	Always	Always	Always

Always

Decode Variables

Bits<1> vm = $encoding[25];
Bits<5> vs2 = $encoding[24:20];
Bits<5> vs1 = $encoding[19:15];
Bits<5> vd = $encoding[11:7];

Execution

Pruned, XLEN == 64
Original