fcvtmod.w.d

Floating-Point Convert Double-Precision to Word with Modulo

This instruction is defined by:

Encoding

Synopsis

The fcvtmod.w.d instruction always rounds towards zero. Bits 31:0 are taken from the rounded, unbounded two’s complement result, then sign-extended to XLEN bits and written to integer register xd. ±∞ and NaN are converted to zero.

Floating-point exception flags are raised the same as they would be for fcvt.w.d with the same input operand.

This instruction is only provided if the D extension is implemented. It is encoded like fcvt.w.d, but with the xs2 field set to 8 and the rm field set to 1 (RTZ). Other rm values are reserved.

Access

M	HS	U	VS	VU
Always	Always	Always	Always	Always

Always

Decode Variables

Bits<5> fs1 = $encoding[19:15];
Bits<3> rm = $encoding[14:12];
Bits<5> xd = $encoding[11:7];

Execution

Pruned, XLEN == 64
Original