pmpcfg2

PMP Configuration Register 2

PMP entry configuration

Attributes

CSR Address

0x3a2

Defining extension

(Sm && NUM_PMP_ENTRIES > 0)

Length

64-bit

Privilege Mode

M

Format

pmpcfg2 format
Figure 1. pmpcfg2 format

Field Summary

Name Location Type Reset Value

pmp8cfg

7:0

RW-R

0

pmp9cfg

15:8

RW-R

0

pmp10cfg

23:16

RW-R

0

pmp11cfg

31:24

RW-R

0

pmp12cfg

39:32

RW-R

0

pmp13cfg

47:40

RW-R

0

pmp14cfg

55:48

RO

0

pmp15cfg

63:56

RO

0

Fields

pmp8cfg

Location

pmpcfg2[7:0]

Description

PMP configuration for entry 8

The bits are as follows:

Name

Location

Description +

L

7

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

MT

6:5

When the Smpmpmt extension is implemented, MT (Memory Type) is a WARL field that overrides the memory type for accesses that match this PMP entry. See the Smpmpmt extension definition for encodings. When the Smpmpmt extension is not implemented, MT is Reserved Writes shall be ignored.

A

4:3

Address matching mode. Encodings:

+ * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NA4 (2) - Naturally aligned four-byte region * NAPOT (3) - Naturally aligned power of two

+

X

2

When clear, instruction fetches cause an Access Fault for the matching region and privilege mode.

W

1

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

0

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RW-R

Read-Write Restricted

Field is writable by software. Only certain values are legal. Writing an illegal value into the field is ignored, and the field retains its prior state.
Reset value

0

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if ((CSR[pmpcfg2].pmp8cfg & 0x80) == 0) {
  Bits<8> new_cfg = csr_value.pmp8cfg;
  Bits<2> a_mode = (new_cfg & 0x18) >> 3;
  if (! {
    if (false || (a_mode == 0x2) || false) {
      return CSR[pmpcfg2].pmp8cfg;
    }
    return new_cfg;
  }
}
return CSR[pmpcfg2].pmp8cfg;

pmp9cfg

Location

pmpcfg2[15:8]

Description

PMP configuration for entry 9

The bits are as follows:

Name

Location

Description +

L

15

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

MT

14:13

When the Smpmpmt extension is implemented, MT (Memory Type) is a WARL field that overrides the memory type for accesses that match this PMP entry. See the Smpmpmt extension definition for encodings. When the Smpmpmt extension is not implemented, MT is Reserved Writes shall be ignored.

A

12:11

Address matching mode. Encodings:

+ * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NA4 (2) - Naturally aligned four-byte region * NAPOT (3) - Naturally aligned power of two

+

X

10

When clear, instruction fetches cause an Access Fault for the matching region and privilege mode.

W

9

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

8

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RW-R

Read-Write Restricted

Field is writable by software. Only certain values are legal. Writing an illegal value into the field is ignored, and the field retains its prior state.
Reset value

0

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if ((CSR[pmpcfg2].pmp9cfg & 0x80) == 0) {
  Bits<8> new_cfg = csr_value.pmp9cfg;
  Bits<2> a_mode = (new_cfg & 0x18) >> 3;
  if (! {
    if (false || (a_mode == 0x2) || false) {
      return CSR[pmpcfg2].pmp9cfg;
    }
    return new_cfg;
  }
}
return CSR[pmpcfg2].pmp9cfg;

pmp10cfg

Location

pmpcfg2[23:16]

Description

PMP configuration for entry 10

The bits are as follows:

Name

Location

Description +

L

23

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

MT

22:21

When the Smpmpmt extension is implemented, MT (Memory Type) is a WARL field that overrides the memory type for accesses that match this PMP entry. See the Smpmpmt extension definition for encodings. When the Smpmpmt extension is not implemented, MT is Reserved Writes shall be ignored.

A

20:19

Address matching mode. Encodings:

+ * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NA4 (2) - Naturally aligned four-byte region * NAPOT (3) - Naturally aligned power of two

+

X

18

When clear, instruction fetches cause an Access Fault for the matching region and privilege mode.

W

17

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

16

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RW-R

Read-Write Restricted

Field is writable by software. Only certain values are legal. Writing an illegal value into the field is ignored, and the field retains its prior state.
Reset value

0

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if ((CSR[pmpcfg2].pmp10cfg & 0x80) == 0) {
  Bits<8> new_cfg = csr_value.pmp10cfg;
  Bits<2> a_mode = (new_cfg & 0x18) >> 3;
  if (! {
    if (false || (a_mode == 0x2) || false) {
      return CSR[pmpcfg2].pmp10cfg;
    }
    return new_cfg;
  }
}
return CSR[pmpcfg2].pmp10cfg;

pmp11cfg

Location

pmpcfg2[31:24]

Description

PMP configuration for entry 11

The bits are as follows:

Name

Location

Description +

L

31

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

MT

30:29

When the Smpmpmt extension is implemented, MT (Memory Type) is a WARL field that overrides the memory type for accesses that match this PMP entry. See the Smpmpmt extension definition for encodings. When the Smpmpmt extension is not implemented, MT is Reserved Writes shall be ignored.

A

28:27

Address matching mode. Encodings:

+ * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NA4 (2) - Naturally aligned four-byte region * NAPOT (3) - Naturally aligned power of two

+

X

26

When clear, instruction fetches cause an Access Fault for the matching region and privilege mode.

W

25

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

24

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RW-R

Read-Write Restricted

Field is writable by software. Only certain values are legal. Writing an illegal value into the field is ignored, and the field retains its prior state.
Reset value

0

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if ((CSR[pmpcfg2].pmp11cfg & 0x80) == 0) {
  Bits<8> new_cfg = csr_value.pmp11cfg;
  Bits<2> a_mode = (new_cfg & 0x18) >> 3;
  if (! {
    if (false || (a_mode == 0x2) || false) {
      return CSR[pmpcfg2].pmp11cfg;
    }
    return new_cfg;
  }
}
return CSR[pmpcfg2].pmp11cfg;

pmp12cfg

Location

pmpcfg2[39:32]

Description

PMP configuration for entry 12

The bits are as follows:

Name

Location

Description +

L

39

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

MT

38:37

When the Smpmpmt extension is implemented, MT (Memory Type) is a WARL field that overrides the memory type for accesses that match this PMP entry. See the Smpmpmt extension definition for encodings. When the Smpmpmt extension is not implemented, MT is Reserved Writes shall be ignored.

A

36:35

Address matching mode. Encodings:

+ * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NA4 (2) - Naturally aligned four-byte region * NAPOT (3) - Naturally aligned power of two

+

X

34

When clear, instruction fetches cause an Access Fault for the matching region and privilege mode.

W

33

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

32

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RW-R

Read-Write Restricted

Field is writable by software. Only certain values are legal. Writing an illegal value into the field is ignored, and the field retains its prior state.
Reset value

0

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if ((CSR[pmpcfg2].pmp12cfg & 0x80) == 0) {
  Bits<8> new_cfg = csr_value.pmp12cfg;
  Bits<2> a_mode = (new_cfg & 0x18) >> 3;
  if (! {
    if (false || (a_mode == 0x2) || false) {
      return CSR[pmpcfg2].pmp12cfg;
    }
    return new_cfg;
  }
}
return CSR[pmpcfg2].pmp12cfg;

pmp13cfg

Location

pmpcfg2[47:40]

Description

PMP configuration for entry 13

The bits are as follows:

Name

Location

Description +

L

47

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

MT

46:45

When the Smpmpmt extension is implemented, MT (Memory Type) is a WARL field that overrides the memory type for accesses that match this PMP entry. See the Smpmpmt extension definition for encodings. When the Smpmpmt extension is not implemented, MT is Reserved Writes shall be ignored.

A

44:43

Address matching mode. Encodings:

+ * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NA4 (2) - Naturally aligned four-byte region * NAPOT (3) - Naturally aligned power of two

+

X

42

When clear, instruction fetches cause an Access Fault for the matching region and privilege mode.

W

41

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

40

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RW-R

Read-Write Restricted

Field is writable by software. Only certain values are legal. Writing an illegal value into the field is ignored, and the field retains its prior state.
Reset value

0

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if ((xlen() == 64) && (CSR[pmpcfg2].pmp13cfg & 0x80) == 0) {
  Bits<8> new_cfg = csr_value.pmp13cfg;
  Bits<2> a_mode = (new_cfg & 0x18) >> 3;
  if (! {
    if (false || (a_mode == 0x2) || false) {
      return CSR[pmpcfg2].pmp13cfg;
    }
    return new_cfg;
  }
}
return CSR[pmpcfg2].pmp13cfg;

pmp14cfg

Location

pmpcfg2[55:48]

Description

PMP configuration for entry 14

The bits are as follows:

Name

Location

Description +

L

55

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

MT

54:53

When the Smpmpmt extension is implemented, MT (Memory Type) is a WARL field that overrides the memory type for accesses that match this PMP entry. See the Smpmpmt extension definition for encodings. When the Smpmpmt extension is not implemented, MT is Reserved Writes shall be ignored.

A

52:51

Address matching mode. Encodings:

+ * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NA4 (2) - Naturally aligned four-byte region * NAPOT (3) - Naturally aligned power of two

+

X

50

When clear, instruction fetches cause an Access Fault for the matching region and privilege mode.

W

49

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

48

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RO

Read-Only

Field has a hardwired value that does not change. Writes to an RO field are ignored.
Reset value

0

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (false) {
  Bits<8> new_cfg = csr_value.pmp14cfg;
  Bits<2> a_mode = (new_cfg & 0x18) >> 3;
  if (! {
    if (false || (a_mode == 0x2) || false) {
      return 8'0;
    }
    return new_cfg;
  }
}
return 8'0;

pmp15cfg

Location

pmpcfg2[63:56]

Description

PMP configuration for entry 15

The bits are as follows:

Name

Location

Description +

L

63

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

MT

62:61

When the Smpmpmt extension is implemented, MT (Memory Type) is a WARL field that overrides the memory type for accesses that match this PMP entry. See the Smpmpmt extension definition for encodings. When the Smpmpmt extension is not implemented, MT is Reserved Writes shall be ignored.

A

60:59

Address matching mode. Encodings:

+ * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NA4 (2) - Naturally aligned four-byte region * NAPOT (3) - Naturally aligned power of two

+

X

58

When clear, instruction fetches cause an Access Fault for the matching region and privilege mode.

W

57

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

56

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RO

Read-Only

Field has a hardwired value that does not change. Writes to an RO field are ignored.
Reset value

0

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (false) {
  Bits<8> new_cfg = csr_value.pmp15cfg;
  Bits<2> a_mode = (new_cfg & 0x18) >> 3;
  if (! {
    if (false || (a_mode == 0x2) || false) {
      return 8'0;
    }
    return new_cfg;
  }
}
return 8'0;