vabd.vv

Vector Single-Width Signed Integer Absolute Difference

This instruction is defined by:

Encoding

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Synopsis

Computes the element-wise absolute difference of two signed integer SEW-bit source operands vs1 and vs2 and writes the result to vd according to mask vm.

Reserved when SEW is neither 8 nor 16.

Access

M HS U VS VU

Always

Always

Always

Always

Always

Decode Variables

Bits<1> vm = $encoding[25];
Bits<5> vs2 = $encoding[24:20];
Bits<5> vs1 = $encoding[19:15];
Bits<5> vd = $encoding[11:7];

Execution

  • Pruned, XLEN == 64

  • Original

VectorState state = vector_state();
if (state.sew != 8 && state.sew != 16) {
  raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
}
VectorLmulType lmul_type = state.lmul_type;
XReg vlen = 17'128;
XReg vlmax;
if (lmul_type == VectorLmulType::Multiply) {
  vlmax = (64'128 << state.log2_lmul) >> state.log2_sew;
} else {
  vlmax = (64'128 >> state.log2_lmul) >> state.log2_sew;
}
for (U32 i = CSR[vstart].VALUE; i < CSR[vl].VALUE; i) {
  U32 start_bit_pos = i * state.sew;
  U32 end_bit_pos = start_bit_pos pass:[+] state.sew - 1;
  if pass:[(]vm == 1'b1 || V[0][i:i] == 1'b1) {
    if pass:[(]$signed(V[vs2][end_bit_pos:start_bit_pos]) >= $signed(++V[vs1][end_bit_pos:start_bit_pos])) {
      V[vd][end_bit_pos:start_bit_pos] = V[vs2][end_bit_pos:start_bit_pos] - V[vs1][end_bit_pos:start_bit_pos];
    } else {
      V[vd][end_bit_pos:start_bit_pos] = V[vs1][end_bit_pos:start_bit_pos] - V[vs2][end_bit_pos:start_bit_pos];
    }
  }
}
CSR[vstart].VALUE = 0;
VectorState state = vector_state();
if (state.sew != 8 && state.sew != 16) {
  raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
}
VectorLmulType lmul_type = state.lmul_type;
XReg vlen = VLEN;
XReg vlmax;
if (lmul_type == VectorLmulType::Multiply) {
  vlmax = (vlen << state.log2_lmul) >> state.log2_sew;
} else {
  vlmax = (vlen >> state.log2_lmul) >> state.log2_sew;
}
for (U32 i = CSR[vstart].VALUE; i < CSR[vl].VALUE; i) {
  U32 start_bit_pos = i * state.sew;
  U32 end_bit_pos = start_bit_pos pass:[+] state.sew - 1;
  if pass:[(]vm == 1'b1 || V[0][i:i] == 1'b1) {
    if pass:[(]$signed(V[vs2][end_bit_pos:start_bit_pos]) >= $signed(++V[vs1][end_bit_pos:start_bit_pos])) {
      V[vd][end_bit_pos:start_bit_pos] = V[vs2][end_bit_pos:start_bit_pos] - V[vs1][end_bit_pos:start_bit_pos];
    } else {
      V[vd][end_bit_pos:start_bit_pos] = V[vs1][end_bit_pos:start_bit_pos] - V[vs2][end_bit_pos:start_bit_pos];
    }
  }
}
CSR[vstart].VALUE = 0;

Exceptions

This instruction may result in the following synchronous exceptions:

  • IllegalInstruction