stvec

Supervisor Trap Vector

Controls where traps jump.

Attributes

CSR Address

0x105

Defining extension

Length

64-bit

Privilege Mode

Figure 1. stvec format

Name Location Type Reset Value

Name	Location	Type	Reset Value
`BASE`	63:2	RW-R	UNDEFINED_LEGAL
`MODE`	1:0	[when,"$array_size(STVEC_MODES) == 1"] RO [when,"$array_size(STVEC_MODES) != 1"] RW-R	UNDEFINED_LEGAL

63:2

RW-R

UNDEFINED_LEGAL

1:0

[when,"$array_size(STVEC_MODES) == 1"] RO

[when,"$array_size(STVEC_MODES) != 1"] RW-R

UNDEFINED_LEGAL

Location: stvec[63:2]
Description: Bits [SXLEN-1:2] of the virtual address of the exception vector for any trap taken into S-mode.

If the base address is written with a non-canonical address (i.e., bits [SXLEN-1:48] do not match bit 47), the write should be ignored.
Type

RW-R	Read-Write Restricted Field is writable by software. Only certain values are legal. Writing an illegal value into the field is ignored, and the field retains its prior state.

Reset value

UNDEFINED_LEGAL

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

return csr_value.BASE;

Location: stvec[1:0]
Description: Vectoring mode for asynchronous interrupts.

0 - Direct, 1 - Vectored

When Direct, all synchronous exceptions and asynchronous interrupts jump to (stvec.BASE << 2).

When Vectored, asynchronous interrupts jump to (stvec.BASE << 2 + scause.CODE*4) while synchronous exceptions continue to jump to (stvec.BASE << 2).
Type

Reset value

UNDEFINED_LEGAL

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if ($array_includes?([1'0, 1'1], csr_value.MODE)) {
  return csr_value.MODE;
}
return UNDEFINED_LEGAL_DETERMINISTIC;