vadd.vv

Vector-vector integer addition

This instruction is defined by:

Encoding

Synopsis

Add source vector register groups from vs1 and vs2 according to mask vm and store results in vd.

Access

M	HS	U	VS	VU
Always	Always	Always	Always	Always

Always

Decode Variables

Bits<1> vm = $encoding[25];
Bits<5> vs2 = $encoding[24:20];
Bits<5> vs1 = $encoding[19:15];
Bits<5> vd = $encoding[11:7];

Execution

Pruned, XLEN == 64
Original

VectorState state = vector_state();
VectorLmulType lmul_type = state.lmul_type;
XReg vlen = 17'128;
XReg vlmax;
if (lmul_type == VectorLmulType::Multiply) {
  vlmax = (64'128 << state.log2_lmul) >> state.log2_sew;
} else {
  vlmax = (64'128 >> state.log2_lmul) >> state.log2_sew;
}
for (U32 i = CSR[vstart].VALUE; i < CSR[vl].VALUE; i++) {
  U32 start_bit_pos = i * state.sew;
  U32 end_bit_pos = start_bit_pos + state.sew - 1;
  V[vd][end_bit_pos:start_bit_pos] = V[vs2][end_bit_pos:start_bit_pos] + V[vs1][end_bit_pos:start_bit_pos];
}
CSR[vstart].VALUE = 0;

VectorState state = vector_state();
VectorLmulType lmul_type = state.lmul_type;
XReg vlen = VLEN;
XReg vlmax;
if (lmul_type == VectorLmulType::Multiply) {
  vlmax = (vlen << state.log2_lmul) >> state.log2_sew;
} else {
  vlmax = (vlen >> state.log2_lmul) >> state.log2_sew;
}
for (U32 i = CSR[vstart].VALUE; i < CSR[vl].VALUE; i++) {
  U32 start_bit_pos = i * state.sew;
  U32 end_bit_pos = start_bit_pos + state.sew - 1;
  V[vd][end_bit_pos:start_bit_pos] = V[vs2][end_bit_pos:start_bit_pos] + V[vs1][end_bit_pos:start_bit_pos];
}
CSR[vstart].VALUE = 0;