vsoxseg2ei32.v

Vector ordered store 2 elements of 32 bits with index

This instruction is defined by:

Encoding

Synopsis

Stores 2 segments of 32-bit elements from vector register vs2 to memory using ordered access pattern with index register vs1, starting at address in xs1 register, using vector mask vm. The effective element width is 32 bits.

Access

M	HS	U	VS	VU
Always	Always	Always	Always	Always

Always

Decode Variables

Bits<1> vm = $encoding[25];
Bits<5> vs2 = $encoding[24:20];
Bits<5> xs1 = $encoding[19:15];
Bits<5> vs3 = $encoding[11:7];

Execution

Pruned, XLEN == 64
Original