hgeie
Hypervisor Guest External Interrupt Enable Register
The hgeie register is an HSXLEN-bit read/write register that contains enable bits for the guest external interrupts at this hart. Guest external interrupt number i corresponds with bit i in hgeie.
Guest external interrupts represent interrupts directed to individual virtual machines at VS-level. If a RISC-V platform supports placing a physical device under the direct control of a guest OS with minimal hypervisor intervention (known as pass-through or direct assignment between a virtual machine and the physical device), then, in such circumstance, interrupts from the device are intended for a specific virtual machine.
Support for guest external interrupts requires an interrupt controller that can collect virtual-machine-directed interrupts separately from other interrupts.
The number of bits implemented in hgeie for guest external interrupts is UNSPECIFIED and may be zero. This number is known as GEILEN. The least-significant bits are implemented first, apart from bit 0. Hence, if GEILEN is nonzero, bits GEILEN:1 shall be writable in hgeie, and all other bit positions shall be read-only zeros.
Register hgeie selects the subset of guest external interrupts that cause a supervisor-level (HS-level) guest external interrupt. The enable bits in hgeie do not affect the VS-level external interrupt signal selected from hgeip by hstatus.VGEIN.
Fields
GEI_ENABLE
- Location
-
hgeie[63:1] - Description
-
Enable bits; see description of hgeie
- Type
RW |
Read-Write Field is writable by software. Any value that fits in the field is acceptable and shall be retained for subsequent reads. |
- Reset value
-
UNDEFINED_LEGAL
- Software write
-
This field has special behavior when written by software (e.g., through csrrw).
When software tries to write
csr_value, the field will be written with the return value of the function below.return 64'15 & csr_value.GEI_ENABLE;