vsip

Virtual Supervisor Interrupt Pending

The vsip register is a VSXLEN-bit read/write register that is VS-mode’s version of the sip CSR. When V=1, instructions that normally access sip instead access vsip. It holds the pending interrupt status for supervisor-level traps in a virtualized environment.

However, interrupts directed to HS-level continue to be indicated in the HS-level sip register, not in vsip, when V=1.

The standard portion (bits 15:0) includes individual interrupt-pending bits.

Attributes

CSR Address	0x244
Virtual CSR Address	0x144
Defining extension	H
Length	64-bit
Privilege Mode	VS

CSR Address

0x244

Virtual CSR Address

0x144

Defining extension

Length

64-bit

Privilege Mode

Format

Figure 1. vsip format

Field Summary

Name Location Type Reset Value

Name	Location	Type	Reset Value
`SSIP`	1	RW-H	UNDEFINED_LEGAL
`STIP`	5	RW-H	UNDEFINED_LEGAL
`SEIP`	9	RW-H	UNDEFINED_LEGAL
`LCOFIP`	13	RW-H	UNDEFINED_LEGAL

SSIP

RW-H

UNDEFINED_LEGAL

STIP

RW-H

UNDEFINED_LEGAL

SEIP

RW-H

UNDEFINED_LEGAL

LCOFIP

RW-H

UNDEFINED_LEGAL

Fields

`SSIP`

Location: vsip[1]
Description: Supervisor Software Interrupt Pending Indicates a pending software interrupt at the supervisor level. Read-only zero when hideleg.VSSI == 0, else aliased to hip.VSSIP.
Type

RW-H	Read-Write with Hardware update Field is writable by software. Any value that fits in the field is acceptable. Hardware also updates the field without an explicit software write.

Reset value

UNDEFINED_LEGAL

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (CSR[hideleg].VSSI == 1) {
  CSR[hip].VSSIP = csr_value.SSIP;
}

`STIP`

Location: vsip[5]
Description: Supervisor Timer Interrupt Pending Indicates a pending timer interrupt at the supervisor level. Read-only zero when hideleg.VSTI == 0, else aliased to hip.VSTIP.
Type

RW-H	Read-Write with Hardware update Field is writable by software. Any value that fits in the field is acceptable. Hardware also updates the field without an explicit software write.

Reset value

UNDEFINED_LEGAL

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (CSR[hideleg].VSTI == 1) {
  CSR[hip].VSTIP = csr_value.STIP;
}

`SEIP`

Location: vsip[9]
Description: Supervisor External Interrupt Pending Indicates a pending external interrupt at the supervisor level. Read-only zero when hideleg.VSEI == 0, else aliased to hip.VSEIP.
Type

RW-H	Read-Write with Hardware update Field is writable by software. Any value that fits in the field is acceptable. Hardware also updates the field without an explicit software write.

Reset value

UNDEFINED_LEGAL

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (CSR[hideleg].VSEI == 1) {
  CSR[hip].VSEIP = csr_value.SEIP;
}

`LCOFIP`

Location: vsip[13]
Description: Local Counter Overflow Interrupt Pending Indicates an overflow of a local counter. Read-only zero when hideleg.LCOFI == 0, else aliased to sip.LCOFIP.
Type

RW-H	Read-Write with Hardware update Field is writable by software. Any value that fits in the field is acceptable. Hardware also updates the field without an explicit software write.

Reset value

UNDEFINED_LEGAL

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (CSR[hideleg].LCOFI == 1) {
  CSR[sip].LCOFIP = csr_value.LCOFIP;
}

Software read

This CSR may return a value that is different from what is stored in hardware.

Pruned
Original

XReg result = 0;
if (CSR[hideleg].VSSI == 1) {
  result[1] = CSR[hip].VSSIP;
}
if (CSR[hideleg].VSTI == 1) {
  result[5] = CSR[hip].VSTIP;
}
if (CSR[hideleg].VSEI == 1) {
  result[9] = CSR[hip].VSEIP;
}
if (CSR[hideleg].LCOFI == 1) {
  result[13] = CSR[sip].LCOFIP;
}
return result;

XReg result = 0;
if (CSR[hideleg].VSSI == 1) {
  result[1] = CSR[hip].VSSIP;
}
if (CSR[hideleg].VSTI == 1) {
  result[5] = CSR[hip].VSTIP;
}
if (CSR[hideleg].VSEI == 1) {
  result[9] = CSR[hip].VSEIP;
}
if (implemented?(ExtensionName::Sscofpmf)) {
  if (CSR[hideleg].LCOFI == 1) {
    result[13] = CSR[sip].LCOFIP;
  }
}
return result;