hgeip

Hypervisor Guest External Interrupt Pending Register

The hgeip register is an HSXLEN-bit read-only register, formatted as that indicates pending guest external interrupts for this hart.

Guest external interrupts represent interrupts directed to individual virtual machines at VS-level. If a RISC-V platform supports placing a physical device under the direct control of a guest OS with minimal hypervisor intervention (known as pass-through or direct assignment between a virtual machine and the physical device), then, in such circumstance, interrupts from the device are intended for a specific virtual machine. Each bit of hgeip summarizes all pending interrupts directed to one virtual hart, as collected and reported by an interrupt controller. To distinguish specific pending interrupts from multiple devices, software must query the interrupt controller.

The number of bits implemented in hgeip and hgeie for guest external interrupts is UNSPECIFIED and may be zero. This number is known as GEILEN. The least-significant bits are implemented first, apart from bit 0. Hence, if GEILEN is nonzero, bits GEILEN:1 shall be writable in hgeie, and all other bit positions shall be read-only zeros in both hgeip and hgeie

Attributes

CSR Address	0xe12
Defining extension	H
Length	64-bit
Privilege Mode	S

CSR Address

0xe12

Defining extension

Length

64-bit

Privilege Mode

Format

Figure 1. hgeip format

Field Summary

Name Location Type Reset Value

Name	Location	Type	Reset Value
`GEI_PENDING`	63:1	RO-H	0

GEI_PENDING

63:1

RO-H

Fields

`GEI_PENDING`

Location: hgeip[63:1]
Description: Pending bits; see description of hgeip
Type

RO-H	Read-Only with Hardware update Writes are ignored. Reads reflect a value dynamically generated by hardware.

Reset value: 0