mhpmcounter5

Machine Hardware Performance Counter 5

Programmable hardware performance counter.

The hpmcounter5 CSR is a read-only shadow of this CSR. Access to hpmcounter5 is controlled with mcounteren.HPM5 , scounteren.HPM5 , and hcounteren.HPM5 as follows:

mcounteren.HPM5	scounteren.HPM5	hcounteren.HPM5	hpmcounter5 behavior
S-mode	U-mode	VS-mode	VU-mode
0	-	-	`IllegalInstruction`	`IllegalInstruction`	`IllegalInstruction`	`IllegalInstruction`
1	0	0	read-only	`IllegalInstruction`	`VirtualInstruction`	`VirtualInstruction`
1	1	0	read-only	read-only	`VirtualInstruction`	`VirtualInstruction`
1	0	1	read-only	`IllegalInstruction`	read-only	`VirtualInstruction`
1	1	1	read-only	read-only	read-only	read-only

mcounteren.HPM5

scounteren.HPM5

hcounteren.HPM5

hpmcounter5 behavior

S-mode

U-mode

VS-mode

VU-mode

IllegalInstruction

read-only

IllegalInstruction

VirtualInstruction

read-only

VirtualInstruction

read-only

IllegalInstruction

read-only

VirtualInstruction

read-only

Attributes

CSR Address	0xb05
Defining extension	(Sm && `HPM_COUNTER_EN[5]` == true)
Length	64-bit
Privilege Mode	M

CSR Address

0xb05

Defining extension

(Sm && HPM_COUNTER_EN[5] == true)

Length

64-bit

Privilege Mode

Format

Figure 1. mhpmcounter5 format

Field Summary

Name Location Type Reset Value

Name	Location	Type	Reset Value
`COUNT`	63:0	RW-H	UNDEFINED_LEGAL

COUNT

63:0

RW-H

UNDEFINED_LEGAL

Fields

`COUNT`

Location: mhpmcounter5[63:0]
Description

Performance counter for event selected in mhpmevent5.EVENT.

+ Increments every time event occurs unless:

+ * mcountinhibit.HPM5 or its alias scountinhibit.HPM5 is set * mhpmevent5.MINH is set and the current privilege level is M * mhpmevent5.SINH or its alias hpmevent5.SINH is set and the current privilege level is (H)S * mhpmevent5.UINH or its alias hpmevent5.UINH is set and the current privilege level is U * mhpmevent5.VSINH or its alias hpmevent5.VSINH is set and the current privilege level is VS * mhpmevent5.VUINH or its alias hpmevent5.VUINH is set and the current privilege level is VU

Unimplemented performance counter. Must be read-only 0 (access does not cause trap).

Type

RW-H	Read-Write with Hardware update Field is writable by software. Any value that fits in the field is acceptable. Hardware also updates the field without an explicit software write.

Reset value: UNDEFINED_LEGAL

Software read

This CSR may return a value that is different from what is stored in hardware.

Pruned
Original

return read_hpm_counter(5);

if (HPM_COUNTER_EN[5]) {
  return read_hpm_counter(5);
} else {
  return 0;
}