hgeie

Hypervisor Guest External Interrupt Enable Register

The hgeie register is an HSXLEN-bit read/write register that contains enable bits for the guest external interrupts at this hart. Guest external interrupt number i corresponds with bit i in hgeie.

Guest external interrupts represent interrupts directed to individual virtual machines at VS-level. If a RISC-V platform supports placing a physical device under the direct control of a guest OS with minimal hypervisor intervention (known as pass-through or direct assignment between a virtual machine and the physical device), then, in such circumstance, interrupts from the device are intended for a specific virtual machine.

Support for guest external interrupts requires an interrupt controller that can collect virtual-machine-directed interrupts separately from other interrupts.

The number of bits implemented in hgeie for guest external interrupts is UNSPECIFIED and may be zero. This number is known as GEILEN. The least-significant bits are implemented first, apart from bit 0. Hence, if GEILEN is nonzero, bits GEILEN:1 shall be writable in hgeie, and all other bit positions shall be read-only zeros.

Register hgeie selects the subset of guest external interrupts that cause a supervisor-level (HS-level) guest external interrupt. The enable bits in hgeie do not affect the VS-level external interrupt signal selected from hgeip by hstatus.VGEIN.

Attributes

Requirement

H

Defining extensions

H

Hypervisor

CSR Address

0x607

Length

* 32 when CSR[mstatus].SXL == 0 * 64 when CSR[mstatus].SXL == 1

Privilege Mode

S

Format

This CSR format changes dynamically.

hgeie Format when CSR[mstatus].SXL == 0
Figure 1. hgeie Format when CSR[mstatus].SXL == 0
hgeie Format when CSR[mstatus].SXL == 1
Figure 2. hgeie Format when CSR[mstatus].SXL == 1

Field Summary

Name Location Type Reset Value

hgeie.GEI_ENABLE

* 31:1 when CSR[mstatus].SXL == 0 * 63:1 when CSR[mstatus].SXL == 1

[when,"NUM_EXTERNAL_GUEST_INTERRUPTS > 0"] RW

[when,"NUM_EXTERNAL_GUEST_INTERRUPTS ⇐ 0"] RO

UNDEFINED_LEGAL

Fields

GEI_ENABLE

Location

  • 31:1 when CSR[mstatus].SXL == 0

  • 63:1 when CSR[mstatus].SXL == 1

Description

Enable bits; see description of hgeie

Type

RW

RO

Reset value

UNDEFINED_LEGAL

Software write

This CSR may store a value that is different from what software attempts to write.

When a software write occurs (e.g., through csrrw), the following determines the written value:

GEI_ENABLE = return ((MXLEN'1 << NUM_EXTERNAL_GUEST_INTERRUPTS) - 1) & csr_value.GEI_ENABLE;