vclmul.vv

Vector carry-less multiply

Performs a carry-less multiply operation on each element in vector register vs2 with the corresponding element in vector register vs1, storing results in vector register vd according to mask vm. This is useful for cryptographic operations.

This instruction must have data-independent timing when extension Zkt is enabled.

Assembly format

vclmul.vv vd, vs2, vs1, vm

Decode Variables

Bits<1> vm = $encoding[25];
Bits<5> vs2 = $encoding[24:20];
Bits<5> vs1 = $encoding[19:15];
Bits<5> vd = $encoding[11:7];

Execution

Encoding

svg

Defining extension

Access

M

Always

Containing profiles

  • Mandatory: RVA20S64, RVA20U64, RVA22S64, RVA22U64, RVA23S64, RVA23U64, RVB23S64, RVB23U64

  • Optional: RVA23U64, RVB23U64