vfncvt.rod.f.f.w

Vector floating-point narrowing conversion with round-to-odd

Converts double-width floating-point elements from vector register vs2 to a single-width floating-point format using round-to-odd mode and stores results in vector register vd, using vector mask vm.

Assembly format

vfncvt.rod.f.f.w vd, vs2, vm

Decode Variables

Bits<1> vm = $encoding[25];
Bits<5> vs2 = $encoding[24:20];
Bits<5> vd = $encoding[11:7];

Execution

Encoding

svg

Defining extension

(Zvl32b || Zvfbfa)

Access

M

Always

Containing profiles

  • Mandatory: None

  • Optional: None