vaesem.vv

Vector AES encryption mix columns

Performs AES encryption mix columns operation on vector register vs2 using vector register vs1, storing results in vector register vd according to mask vm. This is the mix columns operation used in AES encryption.

This instruction must have data-independent timing when extension Zkt is enabled.

Assembly format

vaesem.vv vd, vs2

Decode Variables

Bits<5> vs2 = $encoding[24:20];
Bits<5> vd = $encoding[11:7];

Execution

Encoding

svg

Defining extension

Zvkned

Access

M

Always

Containing profiles

  • Mandatory: RVA20S64, RVA20U64, RVA22S64, RVA22U64, RVA23S64, RVA23U64, RVB23S64, RVB23U64

  • Optional: None