hideleg

Hypervisor Interrupt Delegation Register

Register hideleg is an HSXLEN-bit read/write register. By default, all traps at any privilege level are handled in M-mode, though M-mode usually uses the medeleg and mideleg CSRs to delegate some traps to HS-mode. The hedeleg and hideleg CSRs allow these traps to be further delegated to a VS-mode guest; their layout is the same as medeleg and mideleg. An interrupt that has been delegated to HS-mode (using mideleg) is further delegated to VS-mode if the corresponding hideleg bit is set. Among bits 15:0 of hideleg, bits 10, 6, and 2 (corresponding to the standard VS-level interrupts) are writable, and bits 12, 9, 5, and 1 (corresponding to the standard S-level interrupts) are read-only zeros.

Attributes

Requirement

H

Defining extensions

H

Hypervisor

CSR Address

0x603

Length

* 32 when CSR[mstatus].SXL == 0 * 64 when CSR[mstatus].SXL == 1

Privilege Mode

S

Format

This CSR format changes dynamically.

hideleg Format when CSR[mstatus].SXL == 0
Figure 1. hideleg Format when CSR[mstatus].SXL == 0
hideleg Format when CSR[mstatus].SXL == 1
Figure 2. hideleg Format when CSR[mstatus].SXL == 1

Field Summary

Name Location Type Reset Value

hideleg.SSI

1

RO

0

hideleg.VSSI

2

RW

UNDEFINED_LEGAL

hideleg.STI

5

RO

0

hideleg.VSTI

6

RW

UNDEFINED_LEGAL

hideleg.SEI

9

RO

0

hideleg.VSEI

10

RW

UNDEFINED_LEGAL

hideleg.SGEI

12

RO

0

hideleg.LCOFI

13

RW

UNDEFINED_LEGAL

Fields

SSI

Location

1

Description

Supervisor Software Interrupt

Type

RO

Reset value

0

VSSI

Location

2

Description

Virtual Supervisor Software Interrupt

Type

RW

Reset value

UNDEFINED_LEGAL

STI

Location

5

Description

Supervisor Timer Interrupt

Type

RO

Reset value

0

VSTI

Location

6

Description

Virtual Supervisor Timer Interrupt

Type

RW

Reset value

UNDEFINED_LEGAL

SEI

Location

9

Description

Supervisor External Interrupt

Type

RO

Reset value

0

VSEI

Location

10

Description

Virtual Supervisor External Interrupt

Type

RW

Reset value

UNDEFINED_LEGAL

SGEI

Location

12

Description

Supervisor Guest External Interrupt

Type

RO

Reset value

0

LCOFI

Location

13

Description

Local-Counter-Overfloat Interrupt

Type

RW

Reset value

UNDEFINED_LEGAL

Software write

This CSR may store a value that is different from what software attempts to write.

When a software write occurs (e.g., through csrrw), the following determines the written value:

SSI = csr_value.SSI
VSSI = if (CSR[mideleg].VSSI == 0) {
  return 0;
}
if (csr_value.VSSI == 0) {
  CSR[vsip].SSIP = 0;
  CSR[vsie].SSIE = 0;
}
return csr_value.VSSI;

STI = csr_value.STI
VSTI = if (CSR[mideleg].VSTI == 0) {
  return 0;
}
if (csr_value.VSTI == 0) {
  CSR[vsip].STIP = 0;
  CSR[vsie].STIE = 0;
}
return csr_value.VSTI;

SEI = csr_value.SEI
VSEI = if (CSR[mideleg].VSEI == 0) {
  return 0;
}
if (csr_value.VSEI == 0) {
  CSR[vsip].SEIP = 0;
  CSR[vsie].SEIE = 0;
}
return csr_value.VSEI;

SGEI = csr_value.SGEI
LCOFI = if (CSR[mideleg].LCOFI == 0) {
  return 0;
}
if (csr_value.LCOFI == 0) {
  CSR[vsip].LCOFIP = 0;
  CSR[vsie].LCOFIE = 0;
}
return csr_value.LCOFI;

Software read

This CSR may return a value that is different from what is stored in hardware.

XReg mask = CSR[mideleg].VSSI | CSR[mideleg].VSTI | CSR[mideleg].VSEI | CSR[mideleg].LCOFI;
return $bits(CSR[CSR[hideleg]]) & mask;