vaesdf.vv

Vector AES decryption final round

Performs the final round of AES decryption on vector register vs2 using vector register vs1, storing results in vector register vd according to mask vm. This combines the inverse shift rows, inverse sub bytes, and add round key operations.

This instruction must have data-independent timing when extension Zkt is enabled.

Assembly format

vaesdf.vv vd, vs2

Decode Variables

Bits<5> vs2 = $encoding[24:20];
Bits<5> vd = $encoding[11:7];

Execution

Encoding

svg

Defining extension

Zvkned

Access

M

Always

Containing profiles

  • Mandatory: RVA20S64, RVA20U64, RVA22S64, RVA22U64, RVA23S64, RVA23U64, RVB23S64, RVB23U64

  • Optional: None