vssubu.vv

Vector unsigned subtraction

Performs unsigned subtraction on elements from vector registers vs2 and vs1 and stores results in vector register vd, using vector mask vm.

Assembly format

vssubu.vv vd, vs2, vs1, vm

Decode Variables

Bits<1> vm = $encoding[25];
Bits<5> vs2 = $encoding[24:20];
Bits<5> vs1 = $encoding[19:15];
Bits<5> vd = $encoding[11:7];

Execution

Encoding

svg

Defining extension

Access

M

Always

Containing profiles

  • Mandatory: None

  • Optional: None