vl4re16.v

Vector load 4 elements of 16 bits with register stride

Loads 4 segments of 16-bit elements from memory starting at address in xs1 register with stride in xs2, using vector mask vm, and stores results in vector register vd. The effective element width is 16 bits.

Assembly format

vl4re16.v vd, (xs1)

Decode Variables

Bits<5> xs1 = $encoding[19:15];
Bits<5> vd = $encoding[11:7];

Execution

Encoding

svg

Defining extension

Zvl32b

Access

M

Always

Containing profiles

  • Mandatory: None

  • Optional: None