vmsle.vv

Vector mask less than or equal signed

Sets mask bits where elements in vs2 are less than or equal to elements in vs1 (signed), according to mask vm, and stores results in vd. Element width is determined by SEW setting. Supports vector masking and follows vector tail policy.

Assembly format

vmsle.vv vd, vs2, vs1, vm

Decode Variables

Bits<1> vm = $encoding[25];
Bits<5> vs2 = $encoding[24:20];
Bits<5> vs1 = $encoding[19:15];
Bits<5> vd = $encoding[11:7];

Execution

Encoding

svg

Defining extension

Access

M

Always

Containing profiles

  • Mandatory: None

  • Optional: None